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july 2010 doc id 14395 rev 7 1/120 1 stm8af52xx stm8af6269/8x/ax stm8af51xx stm8af6169/7x/8x/9x/ax automotive 8-bit mcu, with up to 128 kbytes flash, data eeprom, 10-bit adc, timers, lin, can, usart, spi, i 2 c, 3 to 5.5 v features core ?max f cpu : 24 mhz ? advanced stm8a core with harvard architecture and 3-stage pipeline ? average 1.6 cycles/instruction resulting in 10 mips at 16 mhz f cpu for industry standard benchmark memories ? program memory: 32 to 128 kbytes flash program; data retention 20 years at 55 c ? data memory: up to 2 kbytes true data eeprom; endurance 300 kcycles ? ram: 2 kbytes to 6 kbytes clock management ? low-power crystal re sonator oscillator with external clock input ? internal, user-trimmable 16 mhz rc and low-power 128 khz rc oscillators ? clock security system with clock monitor reset and supply management ? wait/slow/auto-wakeup/halt low-power modes with user definable clock gating ? low consumption power-on and power- down reset interrupt management ? nested interrupt controller with 32 vectors ? up to 37 external interrupts on 5 vectors timers ? 2 auto-reload 16-bit pwm timers with up to 3 capcom channels each (ic, oc, pwm) ? multipurpose timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flexible synchronization ? 8-bit ar system timer with 8-bit prescaler ? auto-wakeup timer ? window and standard watchdog timers i/os ? up to 68 user pins inc. 11 high sink i/os ? highly robust i/o design, immune against current injection communication interfaces ? high speed 1 mbit/s can 2.0b interface ? usart with clock output for synchronous operation - lin master mode ? linuart lin 2.1 compliant, master/slave modes with automatic resynchronization ? spi interface up to 10 mbit/s or f cpu /2 ?i 2 c interface up to 400 kbit/s analog to digital converter (adc) ? 10-bit resolution, 2 lsb tue, 1 lsb linearity and up to 16 multiplexed channels operating temperature up to 150 c table 1. device summary (1) 1. in the order code, the letter ?f? applies to devices featuring flash and data eeprom. ?f? is replaced by ?h? for devices with flash only, and by ?p? for devices with fastrom (see table 2 , table 4 , table 3 , table 5 , and figure 50 ). part numbers: stm8af52xx (with can) stm8af52aa, stm8af52a9, stm8af52a8, stm8af528a, stm8af5289, stm8af5288, stm8af5269, stm8af5268 part numbers: stm8af6269/8x/ax stm8af62aa, stm8af62a9, stm8af62a8, stm8af628a, stm8af6289, stm8af6288, stm8af6286, stm8af6269 part numbers: stm8af51xx (with can) stm8af51aa, stm8af51a9, stm8af51a8, stm8af519a, stm8af5199, stm8af5198, stm8af518a, stm8af5189, stm8af5188, stm8af5179, stm8af5178, stm8af5169, stm8af5168 part numbers: stm8af6169/7x/8x/9x/ax stm8af61aa, stm8af61a9, stm8af61a8, stm8af619a, stm8af6199, stm8af6198, stm8af618a, stm8af6189, stm8af6188, stm8af6186, stm8af6179, stm8af6178, stm8af6176, stm8af6169 lqfp80 14x14 lqfp48 7x7 lqfp32 7x7 lqfp64 10x10 www.st.com
contents stm8af52/62xx, stm8af51/61xx 2/120 doc id 14395 rev 7 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 stm8a central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 16 5.2.1 swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 flash program and data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.3 protection of user boot code (ubc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.4 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.2 internal 16 mhz rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.3 internal 128 khz rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.4 internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.5 external clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.6 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7.1 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7.2 auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.3 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
stm8af52/62xx, stm8af51/61xx contents doc id 14395 rev 7 3/120 5.7.4 multipurpose and pwm timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.5 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9.1 universal synchronous/asynchronous receiver transmitter (usart) . . 22 5.9.2 universal asynchronous receiver/transmitter with lin support (linuart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.4 inter integrated circuit (i 2 c) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.5 controller area network interface (becan) . . . . . . . . . . . . . . . . . . . . . . 26 5.10 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.1 i/o register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.2 non volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.4 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.5 clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.6 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.8 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
contents stm8af52/62xx, stm8af51/61xx 4/120 doc id 14395 rev 7 10.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 74 10.3.4 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 76 10.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.7 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.8 tim 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 86 10.3.9 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3.10 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.3.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 97 11 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.1 stm8a core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.1.1 wait for event instruction (wfe) not available . . . . . . . . . . . . . . . . . . . 105 13.1.2 jril and jrih instructions not available . . . . . . . . . . . . . . . . . . . . . . . 105 13.1.3 cpu not returning to halt mode when the al bit is set . . . . . . . . . . . . 106 13.1.4 main program not resuming after isr has reset the al bit . . . . . . . . . 106 13.2 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.2.1 misplaced nack bit when receiving 2 bytes in master mode . . . . . . . 106 13.2.2 data register corrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
stm8af52/62xx, stm8af51/61xx contents doc id 14395 rev 7 5/120 13.2.3 delay in stop bit programming leading to reception of supplementary byte 107 13.2.4 start condition badly generated after misplaced stop . . . . . . . . . . 107 13.3 usart interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.3.1 parity error flag (pe) not correctly set when overrun condition occurs 108 13.4 linuart interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.4.1 framing error with data byte 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.4.2 framing error when receiving an identifier (id) . . . . . . . . . . . . . . . . . . 108 13.4.3 parity error when receiving an identifier (id) . . . . . . . . . . . . . . . . . . . . 108 13.4.4 or flag not correctly set in lin master mode . . . . . . . . . . . . . . . . . . . 109 13.4.5 lin header error when automatic resy nchronization is enabled . . . . . 109 13.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.5.1 hsi rc oscillator cannot be switched of f in run mode . . . . . . . . . . . . . 109 13.6 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.6.1 last bit too short if spi is disabled during communication . . . . . . . . . 109 13.7 becan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.7.1 becan transmission error when sleep mode is entered during transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.7.2 becan woken up from sleep mode with automatic wakeup interrupt . 110 13.7.3 becan time triggered communication mode not supported . . . . . . . . 110 13.7.4 becan transmitted data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.7.5 be can read error in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 112 14.1.1 stice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
list of tables stm8af52/62xx, stm8af51/61xx 6/120 doc id 14395 rev 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8af52xx product line-up with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. stm8af62xx product line-up without can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. stm8af/h/p51xx product line-up with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. stm8af/h/p61xx product line-up without can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. pwm timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. tim4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. legend/abbreviation for table 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. stm8a microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. memory model 128k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12. non volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. cfg_gcr register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. rst_sr register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16. tmu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. clk register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. interrupt software priority registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. external interrupt control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. wwdg register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. iwdg register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 22. awu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23. beep register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 24. tim1 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. tim2 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. tim3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. tim4 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. spi register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. usart register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. linuart register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. adc register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 33. stm8a interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 34. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 35. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 36. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 37. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 38. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 39. operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 40. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 41. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 42. total current consumption in run, wait and slow mode. general conditions for v dd apply. t a = -40 c to 150 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 43. total current consumption in halt and active halt modes. general conditions for v dd apply. t a = -40 c to 55 c unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 44. oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 45. programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 table 46. typical peripheral current consumption v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
stm8af52/62xx, stm8af51/61xx list of tables doc id 14395 rev 7 7/120 table 47. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 48. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 49. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 50. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 51. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 52. program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 53. data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 54. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 56. tim 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 57. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 58. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 59. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 60. adc accuracy for v dda = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 61. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 63. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 64. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 65. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 66. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 67. 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 68. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 69. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 70. product evolution summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 71. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
list of figures stm8af52/62xx, stm8af51/61xx 8/120 doc id 14395 rev 7 list of figures figure 1. stm8a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. flash memory organization of stm8a products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. lqfp 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. lqfp 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 6. lqfp 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8. can register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 9. can page mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 13. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 14. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 72 figure 15. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 72 figure 16. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 73 figure 17. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 73 figure 18. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 19. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 73 figure 20. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 21. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 22. typical hsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 23. typical lsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 24. typical v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 25. typical pull-up resistance r pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 81 figure 26. typical pull-up current i pu vs v dd @ four temperatures (1) . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 27. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 28. typ. v ol @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 29. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 30. typ. v ol @ v dd = 5.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 31. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 32. typ. v ol @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 33. typ. v dd - v oh @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 34. typ. v dd - v oh @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 35. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 36. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 37. typical nrst v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 38. typical nrst pull-up resistance r pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 39. typical nrst pull-up current i pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 40. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 41. spi timing diagram in slave mode and with cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 42. spi timing diagram in slave mode and with cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 43. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 44. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 45. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 46. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 47. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 48. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1
stm8af52/62xx, stm8af51/61xx list of figures doc id 14395 rev 7 9/120 figure 49. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 figure 50. ordering information scheme (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
introduction stm8af52/62xx, stm8af51/61xx 10/120 doc id 14395 rev 7 1 introduction this datasheet refers to the stm8af52xx, stm8af62xx, stm8af 51xx, and stm8af61xx products with 32 to 128 kbytes of program memory. in the order code, the letter ?f? refers to product versions with flash and data eeprom, ?h? to product versions with flash only, and ?p? to product versions with fastrom. the identif iers ?f?, ?h?, and ?p? do not coexist in a given order code. the datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information. for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to stm8a microcontroller family reference manual (rm0009). for information on programming, erasing and protection of the internal flash memory please refer to the stm8 flash programming manual (pm0047). for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044).
stm8af52/62xx, stm8af51/61xx description doc id 14395 rev 7 11/120 2 description the stm8af52xx, stm8af62xx , stm8af51xx, and stm8af61xx automotive 8-bit microcontrollers described in this datasheet offer from 32 kbytes to 128 kbytes of non volatile memory and integrated true data eeprom. the stm8af51xx and stm8af52xx series feature a can interface. all devices of the stm8a product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. reduced system cost ? integrated true data eeprom for up to 300 kwrite/erase cycles ? high system integration level with intern al clock oscillators, watchdog and brown- out reset performance and robustness ? peak performance 20 mips at 24 mhz and average performance 10 mips at 16 mhz cpu clock frequency ? robust i/o, independent watchdogs with separate clock source ? clock security system short development cycles ? applications scalability across a comm on family product architecture with compatible pinout, memory map and modular peripherals. ? full documentation and a wide choice of development tools product longevity ? advanced core and peripherals made in a state-of-the art technology ? native automotive product family operating both at 3.3 v and 5 v supply all stm8a and st7 microcontrollers are supported by the same tools including stvd/stvp development environment, the stice emulator and a low-cost, third party in- circuit debugging tool (for more details, see section 14: stm8 development tools on page 112 ).
product line-up stm8af52/62xx, stm8af51/61xx 12/120 doc id 14395 rev 7 3 product line-up .. table 2. stm8af52xx product line-up with can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af52aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) can, lin(uart) , spi, usart, i2c 72/37 stm8af528a 64 k stm8af52a9 lqfp64 (10x10) 128 k 6 k 2 k 56/36 stm8af5289 64 k 4 k 1.5 k stm8af5269 32 k 2 k 1 k stm8af52a8 lqfp48 (7x7) 128 k 6 k 2 k 10 40/35 stm8af5288 64 k 4 k 1.5 k stm8af5268 32 k 2k 1k 38/35 table 3. stm8af62xx product line-up without can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af62aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart) , spi, usart, i2c 72/37 stm8af628a 64 k stm8af62a9 lqfp64 (10x10) 128 k 56/36 stm8af6289 64 k 4 k 1.5 k stm8af6269 32 k 2 k 1 k stm8af62a8 lqfp48 (7x7) 128 k 6 k 2 k 10 40/35 stm8af6288 64 k 4 k 1.5 k stm8af6286 lqfp32 (7x7) 64 k 4 k 1.5 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart, spi, i2c 25/23
stm8af52/62xx, stm8af51/61xx product line-up doc id 14395 rev 7 13/120 . 2 table 4. stm8af/h/p51xx product line-up with can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/h/p51aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) can, lin(uart) , spi, usart, i2c 72/37 stm8af/h/p519a 96 k stm8af/h/p518a 64 k stm8af/h/p51a9 lqfp64 (10x10) 128 k 56/36 stm8af/h/p5199 96 k stm8af/h/p5189 64 k 4 k 1.5 k stm8af/h/p5179 48 k 3 k stm8af/h/p5169 32 k 2 k 1 k stm8af/h/p51a8 lqfp48 (7x7) 128 k 6 k 2 k 10 40/35 stm8af/h/p5198 96 k stm8af/h/p5188 64 k 4 k 1.5 k stm8af/h/p5178 48 k 3 k stm8af/h/p5168 32 k 2 k 1k 38/35 table 5. stm8af/h/p61xx product line-up without can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/h/p61aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart), spi, usart, i2c 72/37 stm8af/h/p619a 96 k stm8af/h/p618a 64 k stm8af/h/p61a9 lqfp64 (10x10) 128 k 56/36 stm8af/h/p6199 96 k stm8af/h/p6189 64 k 4 k 1.5 k stm8af/h/p6179 48 k 3 k stm8af/h/p6169 32 k 2 k 1 k stm8af/h/p61a8 lqfp48 (7x7) 128 k 6 k 2 k 10 40/35 stm8af/h/p6198 96 k stm8af/h/p6188 64 k 4 k 1.5 k stm8af/h/p6178 48 k 3 k stm8af/h/p6186 lqfp32 (7x7) 64 k 4 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/h/p6176 48 k 3 k
block diagram stm8af52/62xx, stm8af51/61xx 14/120 doc id 14395 rev 7 4 block diagram figure 1. stm8a block diagram xtal 1-24 mhz rc int. 16 mhz rc int. 128 khz stm8a core debug/swim i 2 c spi usart linuart 16-bit pwm timers awu timer reset block reset por pdr clock controller detector clock to peripherals and core 10 mbit/s lin master up to window wdg wdg up to 128 kbyte up to 2 kbytes up to 6 kbytes boot rom 10-bit adc becan 9 capcom reset 400 kbit/s 1 mbit/s master/slave single wire autosynchro debug interf. spi emul. channels program flash 16-bit multi-purpose timer (tim1) (tim2, tim3) 8-bit ar timer (tim4) data eeprom ram up to address and data bus 16 channels
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 15/120 5 product overview this section is intended to describe the family features that are actually implemented in the products covered by this datasheet. for more detailed information on each feature please refer to the stm8a microcontroller family reference manual (rm0009). 5.1 stm8a central processing unit (cpu) the 8-bit stm8a core is a modern cisc core and has been designed for code efficiency and performance. it contains 21 internal regist ers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 5.1.1 architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus with single cycle fetching for most instructions x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter with 16-mbyte linear memory space 16-bit stack pointer with access to a 64 kbyte stack 8-bit condition code register with seven condition flags for the result of the last instruction. 5.1.2 addressing 20 addressing modes indexed indirect addressing mode for look-up tables located anywhere in the address space stack pointer relative addressing mode for efficient implementation of local variables and parameter passing 5.1.3 instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers
product overview stm8af52/62xx, stm8af51/61xx 16/120 doc id 14395 rev 7 5.2 single wire interface module (swim) and debug module (dm) 5.2.1 swim the single wire interface module, swim, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. the interface can be activated in all device operation modes and can be connected to a running device (hot plugging).the maximum data transmission speed is 145 bytes/ms. 5.2.2 debug module the non-intrusive debugging module features a performance close to a full-flavored emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. r/w of ram and peripheral registers in real-time r/w for all resources when th e application is stopped breakpoints on all program-memory instructions (software breakpoints), except the interrupt vector table two advanced breakpoints and 23 predefined breakpoint configurations 5.3 interrupt controller nested interrupts with three software priority levels 24 interrupt vectors with hardware priority five vectors for external interrupts (up to 37 depending on the package) trap and reset interrupts 5.4 flash program and data eeprom 32 kbytes to 128 kbytes of single voltage program flash memory up to 2 kbytes true (n ot emulated) data eeprom read while write: writing in the data memory is possible while executing code in the program memory the device setup is stored in a user option area in the non volatile memory 5.4.1 architecture the memory is organized in blocks of 128 bytes each read granularity: 1 word = 4 bytes write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel writing, erasing, word and block management is handled automatically by the memory interface.
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 17/120 5.4.2 write protection (wp) write protection in application mode is intended to avoid unintentional overwriting of the memory. the write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.3 protection of user boot code (ubc) if the user chooses to update the program memory using a specific boot code to perform in application programming (iap), this boot code needs to be protected against unwanted modification. in the stm8a a memory area of up to 128 kbytes can be protected from overwriting at user option level. other than the standard write protection, the ubc protection can exclusively be modified via the debug interface, the user software cannot modify the ubc protection status. the ubc memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the ubc and nubc option bytes (see section 9: option bytes on page 59 ). figure 2. flash memory organization of stm8a products 5.4.4 read-out protection (rop) the stm8a provides a read-out protection of the code and data memory which can be activated by an option byte setting (see the rop option byte in section 10). the read-out protection prevents reading and writing program memory, data memory and option bytes via the debug module and swim interface. this protection is active in all device operation modes. any attempt to remove the protection by overwriting the rop option byte triggers a global erase of the program and data memory. the rop circuit may provide a temporary access for debugging or failure analysis. the temporary read access is protected by a user defined, 8-byte keyword stored in the option programmable area from 1 kbyte data ubc area program memory area data memory area (first two pages) up to program memory eeprom remains write protected during iap memory write access possible for iap option bytes end - maximum 128 kbytes flash program memory
product overview stm8af52/62xx, stm8af51/61xx 18/120 doc id 14395 rev 7 byte area. this keyword must be entered via the swim interface to temporarily unlock the device. if desired, the temporary unlock mechanism can be permanently disabled by the user throughopt6/nopt6 option bytes. 5.5 clock controller the clock controller distributes the system clock coming from different o scillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. 5.5.1 features clock sources ? internal 16 mhz and 128 khz rc oscillators ? crystal/resonator oscillator ? external clock input reset : after reset the microcontroller restarts by default with an internal 2-mhz clock (16 mhz/8). the clock source and speed can be changed by the application program as soon as the code execution starts. safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. wakeup : in case the device wakes up from low-power modes, the internal rc oscillator (16 mhz/8) is used for quick star tup. after a stabilization time, the device switches to the clock source that was selected before halt mode was entered. clock security system (css) : the css permits monitoring of external clock sources and automatic switching to the internal rc (16 mhz/8) in case of a clock failure. configurable main clock output (cco) : this feature permits to outputs a clock signal for use by the application. 5.5.2 internal 16 mhz rc oscillator default clock after reset 2 mhz (16 mhz/8) fast wakeup time user trimming the register clk_hsitrimr with two trimming bits plus one additional bit for the sign permits frequency tuning by the application program. the adjustment range covers all possible frequency variations versus supply voltage and temperature. this trimming does not change the initial production setting.
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 19/120 5.5.3 internal 128 khz rc oscillator the frequency of this clock is 128 khz and it is independent from the main clock. it drives the independent watchdog or the awu wakeup timer. in systems which do not need independent clock sources for the watchdog counters, the 128 khz signal can be used as the system clock. this configuration has to be enabled by setting an option byte (opt3/opt3n, bit lsi_en). 5.5.4 internal high-speed crystal oscillator the internal high-s peed crystal oscillator can be selected to deliver the main clock in normal run mode. it operates with quartz crystals and ceramic resonators. frequency range: 1 mhz to 24 mhz crystal oscillation mode : preferred fundamental i/os: standard i/o pins multiplexed with oscin, oscout 5.5.5 external clock input an external clock signal can be applied to th e oscin input pin of the crystal oscillator. the frequency range is 0 to 24 mhz. 5.5.6 clock securit y system (css) the clock security system protects against a syste m stall in case of an external crystal clock failure. in case of a clock failure an interrupt is generated and the high-speed internal clock (hsi) is automatically selected with a frequency of 2 mhz (16 mhz/8). 5.6 low-power operating modes the product features various low-power modes: slow mode: prescaled cpu clock, selected peripherals at full clock speed active halt mode: cpu and peripheral clocks are stopped, the device cyclically goes back to run mode, controlled by the awu timer. wakeup through external events is possible. halt mode: cpu and peripheral clocks are stopped, the device remains powered on. wakeup is triggered by an external interrupt. in all modes the cpu and peripherals remain permanently powered on, the system clock is applied only to selected modules. the ram content is preserved and the brown-out reset circuit remains activated. 5.7 timers 5.7.1 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. the watchdog timer activity is controlled by the application program or
product overview stm8af52/62xx, stm8af51/61xx 20/120 doc id 14395 rev 7 option bytes. once the watchdog is activated, it cannot be disabled by the user program without going through reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application timing perfectly. the application software must refresh the counter before time-out and during a limited time window. if the counter is refreshed outside this time window, a reset is issued. independent watchdog timer the independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure. if the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 5.7.2 auto-wakeup counter this counter is used to cyclically wakeup the device in active halt mode. it can be clocked by the internal 128 khz internal low-freq uency rc oscillator or external clock 5.7.3 beeper this function generates a rectangular signal in the range of 1, 2 or 4 khz which can be output on a pin. this is useful when audible sounds without interference need to be generated for use in the application. 5.7.4 multipurpose and pwm timers stm8a devices described in this datasheet, contain up to three 16-bit multipurpose and pwm timers providing nine capcom channels in total. a capcom channel can be used either as input compare, output compare or pwm channel. these timers are named tim1, tim2 and tim3. table 6. pwm timers timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim1 16-bit up/down 1 to 65536 4 3 yes yes yes yes tim2 16-bit up 2 n n = 0 to 15 3 none no no no no tim3 16-bit up 2 n n = 0 to 15 2 none no no no no
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 21/120 tim1: multipurpose pwm timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and bridge driver. 16-bit up, down and up/down ar (auto-reload) counter with 16-bit fractional prescaler. four independent capcom channels configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output trigger module which allows the interaction of tim1 with other on-chip peripherals. in the present implementation it is possible to trigger the adc upon a timer event. external trigger to change the timer behavior depending on external signals break input to force the timer outputs into a defined state three complementary outputs with adjustable dead time interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break tim2 and tim3: 16-bit pwm timers 16-bit auto-reload up-counter 15-bit prescaler adjustable to fixed power of two ratios 1?32768 timers with three or two individually configurable capcom channels interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 5.7.5 system timer the typical usage of this timer (tim4) is the generation of a clock tick. 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 clock source: master clock interrupt source: 1 x overflow/update table 7. tim4 timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim4 8-bit up 2 n n = 0 to 7 0 none no no no no
product overview stm8af52/62xx, stm8af51/61xx 22/120 doc id 14395 rev 7 5.8 analog to digital converter (adc) the stm8a products described in this datasheet contain a 10-bit successive approximation adc with up to 16 multiplexed input channels, depending on the package. adc features: 10-bit resolution single and continuous conversion modes programmable prescaler: f master divided by 2 to 18 conversion trigger on timer events, and external events interrupt generation at end of conversion selectable alignment of 10-bit data in 2 x 8 bit result registers shadow registers for data consistency adc input range: vssa = vin = vdda schmitt-trigger on analog inputs can be disabled to reduce power consumption 5.9 communication interfaces 5.9.1 universal synchronous/asynch ronous receiver tr ansmitter (usart) the devices covered by this datasheet contain one usart interface. the usart can operate in standard sci mode (serial communication interface, asynchronous) or in spi emulation mode. it is equipped with a 16 bit fractional prescaler. it features lin master support. detailed feature list: full duplex, asynchronous communications nrz standard format (mark/space) high-precision baud rate generator system ? common programmable transmit and receive baud rates up to f master /16 programmable data word length (8 or 9 bits) configurable stop bits: support for 1 or 2 stop bits lin master mode: ? lin break and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for readback checking. transmitter clock output for synchronous communication separate enable bits for transmitter and receiver transfer detection flags: ? receive buffer full ? transmit buffer empty ? end of transmission flags parity control: ? transmits parity bit ? checks parity of received data byte
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 23/120 four error detection flags: ? overrun error ? noise error ?frame error ? parity error six interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? parity error ? lin break and delimiter detection two interrupt vectors: ? transmitter interrupt ? receiver interrupt reduced power consumption mode wakeup from mute mode (by idle line detection or address mark detection) two receiver wakeup modes: ? address bit (msb) ? idle line 5.9.2 universal asynchronous recei ver/transmitter with lin support (linuart) the devices covered by this datasheet contain one linuart interface. the interface is available on all the supported packages. the linuart is an asynchronous serial communication interface which supports extensive lin functions tailored for lin slave applications. in lin mode it is compliant to the lin standards rev 1.2 to rev 2.1. detailed feature list: lin mode master mode lin break and delimiter generation lin break and delimiter detection with separate flag and interrupt source for read back checking.
product overview stm8af52/62xx, stm8af51/61xx 24/120 doc id 14395 rev 7 slave mode autonomous header handling ? one single interrupt per valid header mute mode to filter responses identifier parity error checking lin automatic resynchronizat ion, allowing operat ion with internal rc oscillator (hsi) clock source break detection at any time, even during a byte reception header errors detection: ? delimiter too short ? synch field error ? deviation error (if automatic resynchronization is enabled) ? framing error in synch field or identifier field ? header time-out uart mode full duplex, asynchronous communications - nrz standard format (mark/space) high-precision baud rate generator ? a common programmable transmit and receive baud rates up to f master /16 programmable data word length (8 or 9 bits) ? 1 or 2 stop bits ? parity control separate enable bits for transmitter and receiver error detection flags reduced power consumption mode multi-processor communication - enter mute mode if address match does not occur wakeup from mute mode (by idle line detection or address mark detection) two receiver wakeup modes: ? address bit (msb) ? idle line
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 25/120 5.9.3 serial peripheral interface (spi) the devices covered by this datasheet contain one spi. the spi is available on all the supported packages. maximum speed: 8 mbit/s or f master /2 both for master and slave full duplex synchronous transfers simplex synchronous transfers on two lines with a possible bidirectional data line master or slave operation - selectable by hardware or software crc calculation 1 byte tx and rx buffer slave mode/master mode management by hardware or software for both master and slave programmable clock polarity and phase programmable data order with msb-first or lsb-first shifting dedicated transmission a nd reception flags with interrupt capability spi bus busy status flag hardware crc feature for reliable communication: ? crc value can be transmitted as last byte in tx mode ? crc error checking for last received byte 5.9.4 inter integrated circuit (i 2 c) interface the devices covered by this datasheet contain one i 2 c interface. the inte rface is available on all the supported packages. i 2 c master features: ? clock generation ? start and stop generation i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection generation and detection of 7-bit/10-bit addressing and general call supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) status flags: ? transmitter/receiver mode flag ? end-of-byte transmission flag ?i 2 c busy flag error flags: ? arbitration lost condition for master mode ? acknowledgement failure after address/data transmission ? detection of misplaced start or stop condition ? overrun/underrun if clock stretching is disabled
product overview stm8af52/62xx, stm8af51/61xx 26/120 doc id 14395 rev 7 interrupt: ? successful address/data communication ? error condition ? wakeup from halt wakeup from halt on address detection in slave mode 5.9.5 controller area network inte rface (becan) the becan controller (basic enhanced can), in terfaces the can network and supports the can protocol version 2.0a and b. it is equipped with a receive fifo and a very versatile filter bank. together with a filter match index, this allows a very efficient message handling in today?s car network architectures. the cpu is significantly unloaded. the maximum transmission speed is 1 mbit/s. transmission three transmit mailboxes configurable transmit priority by identifier or order request reception 11- and 29-bit id 1 receive fifo (3 messages deep) software-efficient mailbox mapping at a unique address space fmi (filter match index) stored with message for quick message association configurable fifo overrun time stamp on sof reception 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit id or 48 filters for 11-bit id. filtering modes (mixable): ? mask mode permitting id range filtering ? id list mode interrupt management maskable interrupt software-efficient mailbox mapping at a unique address space 5.10 input/output specifications the product features four i/o types: standard i/o 2 mhz fast i/o up to 10 mhz high sink 8 ma, 2 mhz true open drain (i 2 c interface) to decrease emi (electromagnetic interference), high sink i/os have a limited maximum slew rate. the rise and fall times are similar to those of standard i/os.
stm8af52/62xx, stm8af51/61xx product overview doc id 14395 rev 7 27/120 the analog inputs are equipped with a low leakage analog switch. additionally, the schmitt- trigger input stage on the analog i/os can be disabled in order to reduce the device standby consumption. stm8a i/os are designed to withstand current injection. for a negative injection current of 4 ma, the resulting leakage current in the adjacent input does not exceed 1 a. thanks to this feature, external protection diodes against current injection are no longer required.
pinouts and pin description stm8af52/62xx, stm8af51/61xx 28/120 doc id 14395 rev 7 6 pinouts and pin description 6.1 package pinouts figure 3. lqfp 80-pin pinout 1. the can interface is only available on the stm8af/h/p51xx and stm8af52xx product lines. 2. hs stands for high sink capability. pd4 (hs)/tim2_cc1/beep 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pi4 pi3 pi2 pi1 pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pg6 pg5 pi5 pi0 pg4 pg3 pg2 pc7/spi_miso v ssio_2 v ddio_1 tim2_cc3/pa3 usart_rx/pa4 usart_tx/pa5 ain12/pf4 v ssio_1 v ss vcap v dd usart_ck/pa6 (hs) ph0 ( hs) ph1 ph2 ph3 ain15/pf7 ain14/pf6 ain13/pf5 nrst oscin/pa1 oscout/pa2 ain5/pb5 ain4/pb4 ain1/pb1 ain0/pb0 ain8/pe7 v ref- ain10/pf0 ain7/pb7 ain6/pb6 tim1_etr/ph4 tim1_ncc3/ph5 tim1_ncc2/ph6 40 ain9/pe6 21 22 24 23 ain11/pf3 v ref+ v dda v ssa pd0 (hs)/tim3_cc2 pe2/i 2c_sda pe3/tim1_bkin pe4 pg7 pd7/tli pd6/linuart_rx pd5/linuart_tx pi7 pi6 pd2 (hs)/tim3_cc1 pd1 (hs)/swim pc5/spi_sck pc6/spi_mosi pg0/can_tx (1) pg1/can_rx (1) pe0/clk_cco pd3 (hs)/tim2_cc2 ain3/pb3 ain2/pb2 pc0/adc_etr pe5/spi_nss tim1_ncc1/ph7 v ddio_2 pe1/i2c_scl
stm8af52/62xx, stm8af51/61xx pinouts and pin description doc id 14395 rev 7 29/120 figure 4. lqfp 64-pin pinout 1. the can interface is only available on the stm8af/h/p51xx and stm8af52xx product lines. 2. hs stands for high sink capability. v ref- ain10/pf0 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 ain8/pe7 ain9/pe6 ain11/pf3 v ref+ v dda v ssa 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss vcap v dd v ddio_1 tim2_cc3/pa3 usart_rx/pa4 usart_tx/pa5 usart_ck/pa6 ain15/pf7 ain14/pf6 ain13/pf5 ain12/pf4 nrst oscin/pa1 oscout/pa2 v ssio_1 pg1/can_rx (1) pg0/can_tx (1) pc7/spi_miso pc6/spi_mosi v ddio_2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pe5/spi_nss pi0 pg4 pg3 pg2 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1 pd1 (hs)/swim pd0 (hs)/tim3_cc2 pe0/clk_cco pe1/i2c_scl pe2/i2c_sda pe3/tim1_bkin pe4 pg7 pg6 pg5 pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/ beep
pinouts and pin description stm8af52/62xx, stm8af51/61xx 30/120 doc id 14395 rev 7 figure 5. lqfp 48-pin pinout 1. the can interface is only available on the stm8af/h/p51xx and stm8af52xx product lines. 2. hs stands for high sink capability. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 usart_ck/pa6 ain8/pe7 pc1 (hs)/tim1_cc1 pe5/spi_nss pg1/can_rx ain9/pe6 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1 pe0/clk_cco pe1/i 2 c_scl pe2/i 2 c_sda pe3/tim1_bkin pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/beep pd1 (hs)/swim pd0 (hs)/tim3_cc2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pg0/can_tx pc7/spi_miso pc6/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 tim2_cc3/pa3 usart_rx/pa4 usart_tx/pa5 nrst oscin/pa1 oscout/pa2 v ssio_1
stm8af52/62xx, stm8af51/61xx pinouts and pin description doc id 14395 rev 7 31/120 figure 6. lqfp 32-pin pinout 1. hs stands for high sink capability. table 8. legend/abbreviation for table 9 type i= input, o = output, s = power supply level input cm = cmos (standard for all i/os) output hs = high sink (8 ma) output speed o1 = standard (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull i2c_scl/ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 v dda v ssa i2c_sda/ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pe5/spi_nss pc7/spi_miso pc6/spi_mosi pc5/spi_sck pc4 (hs)/tim1_cc4 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1/tim2_cc3 pd1 (hs)/swim pd0 (hs)/tim3_cc2/clk_cco/tim1_brk pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/beep
pinouts and pin description stm8af52/62xx, stm8af51/61xx 32/120 doc id 14395 rev 7 table 9. stm8a microcontroller family pin description pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp 1 1 1 1 nrst i/o - x ? ? ? ? ? reset ? 2222 pa1/oscin (1) i/o x x ? ? o1 x x port a1 resonator/ crystal in ? 3 3 3 3 pa2/oscout i/o x x x ? o1 x x port a2 resonator/ crystal out ? 444- v ssio_1 s ? ? ? ? ? ? ? i/o ground ? 5554 v ss s ? ? ? ? ? ? ? digital ground ? 6 6 6 5 vcap s ? ? ? ? ? ? ? 1.8 v regulator capacitor ? 7776 v dd s ? ? ? ? ? ? ? digital power supply ? 8887 v ddio_1 s ? ? ? ? ? ? ? i/o power supply ? 9 9 9 - pa3/tim2_cc3 i/o x x x ? o1 x x port a3 timer 2 - channel 3 tim3_cc1 [afr1] 10 10 10 - pa4/usart_rx i/o x x x ? o3 x x port a4 usart receive ? 11 11 11 - pa5/usart_tx i/o x x x ? o3 x x port a5 usart transmit ? 12 12 12 - pa6/usart_ck i/o x x x ? o3 x x port a6 usart synchronous clock ? 13--- ph0 i/oxx?hso3xxport h0 ? ? 14--- ph1 i/oxx?hso3xxport h1 ? ? 15 - - - ph2 i/o x x ? ? o1 x x port h2 ? ? 16 - - - ph3 i/o x x ? ? o1 x x port h3 ? ? 17 13 - - pf7/ain15 i/o x x ? ? o1 x x port f7 analog input 15 ? 18 14 - - pf6/ain14 i/o x x ? ? o1 x x port f6 analog input 14 ? 19 15 - - pf5/ain13 i/o x x ? ? o1 x x port f5 analog input 13 ? 20 16 - 8 pf4/ain12 i/o x x ? ? o1 x x port f4 analog input 12 ? 21 17 - - pf3/ain11 i/o x x ? ? o1 x x port f3 analog input 11 ? 22 18 - - v ref+ s??????? adc positive reference voltage ?
stm8af52/62xx, stm8af51/61xx pinouts and pin description doc id 14395 rev 7 33/120 23 19 13 9 v dda s ? ? ? ? ? ? ? analog power supply ? 24 20 14 10 v ssa s ? ? ? ? ? ? ? analog ground ? 25 21 - - v ref- s??????? adc negative reference voltage ? 26 22 - - pf0/ain10 i/o x x ? ? o1 x x port f0 analog input 10 ? 27 23 15 - pb7/ain7 i/o x x x ? o1 x x port b7 analog input 7 ? 28 24 16 - pb6/ain6 i/o x x x ? o1 x x port b6 analog input 6 ? 29 25 17 11 pb5/ain5 i/o x x x ? o1 x x port b5 analog input 5 i 2 c_sda [afr6] 30 26 18 12 pb4/ain4 i/o x x x ? o1 x x port b4 analog input 4 i 2 c_scl [afr6] 31 27 19 13 pb3/ain3 i/o x x x ? o1 x x port b3 analog input 3 tim1_etr [afr5] 32 28 20 14 pb2/ain2 i/o x x x ? o1 x x port b2 analog input tim1_ncc 3 [afr5] 33 29 21 15 pb1/ain1 i/o x x x ? o1 x x port b1 analog input 1 tim1_ncc 2 [afr5] 34 30 22 16 pb0/ain0 i/o x x x ? o1 x x port b0 analog input 0 tim1_ncc 1 [afr5] 35 - - - ph4/tim1_etr i/o x x ? ? o1 x x port h4 timer 1 - trigger input ? 36--- ph5/ tim1_ncc3 i/o x x ? ? o1 x x port h5 timer 1 - inverted channel 3 ? 37--- ph6/ tim1_ncc2 i/o x x ? ? o1 x x port h6 timer 1 - inverted channel 2 ? 38--- ph7/ tim1_ncc1 i/o x x ? ? o1 x x port h7 timer 1 - inverted channel 2 ? 39 31 23 - pe7/ain8 i/o x x ? ? o1 x x port e7 analog input 8 ? 40 32 24 pe6/ain9 i/o x x x ? o1 x x port e7 analog input 9 ? 41 33 25 17 pe5/spi_nss i/o x x x ? o1 x x port e5 spi master/ slave select ? table 9. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8af52/62xx, stm8af51/61xx 34/120 doc id 14395 rev 7 42 - - - pc0/adc_etr i/o x x x ? o1 x x port c0 adc trigger input ? 43 34 26 18 pc1/tim1_cc1 i/o x x x hs o3 x x port c1 timer 1 - channel 1 ? 44 35 27 19 pc2/tim1_cc2 i/o x x x hs o3 x x port c2 timer 1- channel 2 ? 45 36 28 20 pc3/tim1_cc3 i/o x x x hs o3 x x port c3 timer 1 - channel 3 ? 46 37 29 21 pc4/tim1_cc4 i/o x x x hs o3 x x port c4 timer 1 - channel 4 ? 47 38 30 22 pc5/spi_sck i/o x x x ? o3 x x port c5 spi clock ? 48 39 31 - v ssio_2 s ? ? ? ? ? ? ? i/o ground ? 49 40 32 - v ddio_2 s ? ? ? ? ? ? ? i/o power supply ? 50 41 33 23 pc6/spi_mosi i/o x x x ? o3 x x port c6 spi master out/ slave in ? 51 42 34 24 pc7/spi_miso i/o x x x ? o3 x x port c7 spi master in/ slave out ? 52 43 35 - pg0/can_tx i/o x x ? ? o1 x x port g0 can transmit ? 53 44 36 - pg1/can_rx i/o x x ? ? o1 x x port g1 can receive ? 54 45 - - pg2 i/o x x ? ? o1 x x port g2 ? ? 55 46 - - pg3 i/o x x ? ? o1 x x port g3 ? ? 56 47 - - pg4 i/o x x ? ? o1 x x port g4 ? ? 57 48 - - pi0 i/o x x ? ? o1 x x port i0 ? ? 58 - - - pi1 i/o x x ? ? o1 x x port i1 ? ? 59 - - - pi2 i/o x x ? ? o1 x x port i2 ? ? 60 - - - pi3 i/o x x ? ? o1 x x port i3 ? ? 61 - - - pi4 i/o x x ? ? o1 x x port i4 ? ? 62 - - - pi5 i/o x x ? ? o1 x x port i5 ? ? 63 49 - - pg5 i/o x x ? ? o1 x x port g5 ? ? 64 50 - - pg6 i/o x x ? ? o1 x x port g6 ? ? 65 51 - - pg7 i/o x x ? ? o1 x x port g7 ? ? 66 52 - - pe4 i/o x x x ? o1 x x port e4 ? ? table 9. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8af52/62xx, stm8af51/61xx pinouts and pin description doc id 14395 rev 7 35/120 67 53 37 - pe3/tim1_bkin i/o x x x ? o1 x x port e3 timer 1 - break input ? 68 54 38 - pe2/i 2 c_sda i/o x x x ? o1 t (2) -port e2 i 2 c data ? 69 55 39 - pe1/i 2 c_scl i/o x x x ? o1 t (2) -port e1 i 2 c clock ? 70 56 40 - pe0/clk_cco i/o x x x ? o3 x x port e0 configurable clock output ? 71 - - - pi6 i/o x x ? ? o1 x x port i6 ? ? 72 - - - pi7 i/o x x ? ? o1 x x port i7 ? ? 73 57 41 25 pd0/tim3_cc2 i/o x x x hs o3 x x port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 74 58 42 26 pd1/swim i/o x x x hs o4 x x port d1 swim data interface ? 75 59 43 27 pd2/tim3_cc1 i/o x x x hs o3 x x port d2 timer 3 - channel 1 tim2_cc3 [afr1] 76 60 44 28 pd3/tim2_cc2 i/o x x x hs o3 x x port d3 timer 2 - channel 2 adc_etr [afr0] 77 61 45 29 pd4/tim2_cc1/ beep i/o x x x hs o3 x x port d4 timer 2 - channel 1 beep output [afr7] 78 62 46 30 pd5/ linuart_tx i/o x x x ? o1 x x port d5 linuart data transmit ? 79 63 47 31 pd6/ linuart_rx i/o x x x ? o1 x x port d6 linuart data receive ? 80 64 48 32 pd7/tli (3) i/o x x x ? o1 x x port d7 top level interrupt ? 1. in halt/active halt mode, th is pin behaves as follows: - the input/output path is disabled. - if the hse clock is used for wakeup, the internal weak pull-up is disabled. - if the hse clock is off, the internal weak pull-up setting is used. it is configured through px_cr1[7:0] bits of the corresponding port control register. px_cr1 [7:0] bits must be set correctly to ensur e that the pin is not left floating in halt/active halt mode. 2. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented) 3. if this pin is configured as interru pt pin, it will trigger the tli. table 9. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8af52/62xx, stm8af51/61xx 36/120 doc id 14395 rev 7 6.2 alternate function remapping as shown in the rightmost column of ta bl e 9 , some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 9: option bytes on page 59 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding pe ripheral must be enabled in the peripheral registers. alternate function remapping d oes not effect gpio capabilitie s of the i/o ports (see the gpio section of the stm8a microcontroller family reference manual, rm0009).
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 37/120 7 memory and register map 7.1 memory map figure 7. register and memory map table 10. memory model 128k program memory size program memory end address ram size ram end address stack roll-over address 128k 27fffh 6k 17ffh 1400h 96k 1ffffh 6k 17ffh 1400h 64k 17fffh 4k 0fffh n/a (1) 1. if the device is containing the super set silicon (s alestype contains sss), the roll-over address is the same as on the 128k device. for more information on stack handling refer to section 2.1.2 in the reference manual rm0009. for more information on salestype composition, refer to section 13 in the present document. 48k 13fffh 3k 0bffh n/a (1) 32k 0ffffh 2k 07ffh n/a (1) up to 2 kbytes data eeprom option bytes hw registers 2 kbytes boot rom cpu registers it vectors up to 128 kbytes 00 0000 ram end address 00 4000 00 4800 00 5000 00 5800 00 6000 00 6800 00 7f00 00 8000 memory end address 00 8080 reserved reserved stack up to 6 kbytes ram 00 4900 reserved flash program memory
memory and register map stm8af52/62xx, stm8af51/61xx 38/120 doc id 14395 rev 7 7.2 register map in this section the memory and register map of the devices covered by this datasheet is described. for a detailed description of the functionality of the registers, refer to the reference manual rm009. 7.2.1 i/o register map table 11. i/o port hardware register map address block register label register name reset status 00 5000h port a pa_odr port a data output latch register 00h 00 5001h pa_idr port a input pin value register 00h 00 5002h pa_ddr port a data direction register 00h 00 5003h pa_cr1 port a control register 1 00h 00 5004h pa_cr2 port a control register 2 00h 00 5005h port b pb_odr port b data output latch register 00h 00 5006h pb_idr port b input pin value register 00h 00 5007h pb_ddr port b data direction register 00h 00 5008h pb_cr1 port b control register 1 00h 00 5009h pb_cr2 port b control register 2 00h 00 500ah port c pc_odr port c data output latch register 00h 00 500bh pb_idr port c input pin value register 00h 00 500ch pc_ddr port c data direction register 00h 00 500dh pc_cr1 port c control register 1 00h 00 500eh pc_cr2 port c control register 2 00h 00 500fh port d pd_odr port d data output latch register 00h 00 5010h pd_idr port d input pin value register 00h 00 5011h pd_ddr port d data direction register 00h 00 5012h pd_cr1 port d control register 1 02h 00 5013h pd_cr2 port d control register 2 00h 00 5014h port e pe_odr port e data output latch register 00h 00 5015h pe_idr port e input pin value register 00h 00 5016h pe_ddr port e data direction register 00h 00 5017h pe_cr1 port e control register 1 00h 00 5018h pe_cr2 port e control register 2 00h
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 39/120 7.2.2 non volatile memory 00 5019h port f pf_odr port f data output latch register 00h 00 501ah pf_idr port f input pin value register 00h 00 501bh pf_ddr port f data direction register 00h 00 501ch pf_cr1 port f control register 1 00h 00 501dh pf_cr2 port f control register 2 00h 00 501eh port g pg_odr port g data output latch register 00h 00 501fh pg_idr port g input pin value register 00h 00 5020h pg_ddr port g data direction register 00h 00 5021h pg_cr1 port g control register 1 00h 00 5022h pg_cr2 port g control register 2 00h 00 5023h port h ph_odr port h data output latch register 00h 00 5024h ph_idr port h input pin value register 00h 00 5025h ph_ddr port h data direction register 00h 00 5026h ph_cr1 port h control register 1 00h 00 5027h ph_cr2 port h control register 2 00h 00 5028h port i pi_odr port i data output latch register 00h 00 5029h pi_idr port i input pin value register 00h 00 502ah pi_ddr port i data direction register 00h 00 502bh pi_cr1 port i control register 1 00h 00 502ch pi_cr2 port i control register 2 00h table 11. i/o port hardware register map (continued) address block register label register name reset status table 12. non volatile memory address register name 7 6 5 4 3 2 1 0 00 505ah flash_cr1 reset value - 0 - 0 - 0 - 0 halt 0 ahalt 0 ie 0 fix 0 00 505bh flash_cr2 reset value opt 0 wprg 0 erase 0 fprg 0 - 0 - 0 - 0 prg 0 00 505ch flash_ncr2 reset value nopt 1 nwprg 1 nerase 1 nfprg 1 - 1 - 1 - 1 nprg 1 00 505dh flash_fpr reset value wpb7 0 wpb6 0 wpb5 0 wpb4 0 wpb3 0 wpb2 0 wpb1 0 wpb0 0 00 505eh flash_nfpr reset value nwpb7 1 nwpb6 1 nwpb5 1 nwpb4 1 nwpb3 1 nwpb2 1 nwpb1 1 nwpb0 1
memory and register map stm8af52/62xx, stm8af51/61xx 40/120 doc id 14395 rev 7 7.2.3 cpu registers 7.2.4 miscellaneous registers global configuration register 00 505fh flash_iapsr reset value - 0 hvoff 1 - 0 - 0 dul 0 eop 0 pul 0 wr_pg_dis 0 00 5060h to 00 5061h reserved 00 5062h flash_pukr reset value puk7 0 puk6 0 puk5 0 puk4 0 puk3 0 puk2 0 puk1 0 puk0 0 00 5063h reserved 00 5064h flash_dukr reset value duk7 0 duk6 0 duk5 0 duk4 0 duk3 0 duk2 0 duk1 0 duk0 0 table 12. non volatile memory (continued) address register name 7 6 5 4 3 2 1 0 table 13. cpu registers address block register label register name reset status 00 7f00h cpu (1) a accumulator 00h 00 7f01h pce program counter extended 00h 00 7f02h pch program counter high 80h 00 7f03h pcl program counter low 00h 00 7f04h xh x index register high 00h 00 7f05h xl x index register low 00h 00 7f06h yh y index register high 00h 00 7f07h yl y index register low 00h 00 7f08h sph stack pointer high 17h (2) 00 7f09h spl stack pointer low ffh 00 7f0ah cc condition code register 28h 1. accessible by debug module only 2. product dependent value, see figure 7: register and memory map . table 14. cfg_gcr register map address register name 7 6 5 4 3 2 1 0 00 7f60h cfg_gcr reset value - 0 - 0 - 0 - 0 - 0 - 0 al 0 swd 0
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 41/120 reset status register temporary memory unprotection key registers 7.2.5 clock and clock controller table 15. rst_sr register map address register name 7 6 5 4 3 2 1 0 00 50b3h rst_sr reset value - x - x - x emcf x swimf x illopf x iwdgf x wwdgf x table 16. tmu register map and reset values address register name 7 6 5 4 3 2 1 0 00 5800h tmu_k1 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5801h tmu_k2 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5802h tmu_k3 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5803h tmu_k4 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5804h tmu_k5 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5805h tmu_k6 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5807h tmu_k8 reset value k7 0 k6 0 k5 0 k4 0 k3 0 k2 0 k1 0 k0 0 00 5808h tmu_csr reset value - 0 - 0 - 0 - 0 rops 0 timue 0 tmub 0 tmus 0 table 17. clk register map and reset values address register name 76543210 00 50c0h clk_ickr reset value - 0 - 0 swuah 0 lsirdy 0 lsien 0 fhwu 0 hsirdy 0 hsien 1 00 50c1h clk_ eckr reset value - 0 - 0 - 0 - 0 - 0 - 0 hserdy 0 hseen 0 00 50c2h reserved
memory and register map stm8af52/62xx, stm8af51/61xx 42/120 doc id 14395 rev 7 00 50c3h clk_ cmsr reset value ckm7 1 ckm6 1 ckm5 1 ckm4 0 ckm3 0 ckm2 0 ckm1 0 ckm0 1 00 50c4h clk_swr reset value swi7 1 swi6 1 swi5 1 swi4 0 swi3 0 swi2 0 swi1 0 swi0 1 00 50c5h clk_ swcr reset value - x - x - x - x swif 0 swien 0 swen 0 swbsy 0 00 50c6h clk_ ckdivr reset value - 0 - 0 - 0 hsidiv1 1 hsidiv0 1 cpudiv2 0 cpudiv1 0 cpudiv 0 00 50c7h clk_ pckenr1 reset value pck en17 1 pck en16 1 pck en15 1 pck en14 1 pck en13 1 pck en12 1 pck en11 1 pck en10 1 00 50c8h clk_ cssr reset value - 0 - 0 - 0 - 0 cssd 0 cssdie 0 aux 0 cssen 0 00 50c9h clk_ ccor reset value - 0 ccobsy 0 ccordy 0 cco sel3 0 cco sel2 0 cco sel1 0 cco sel0 0 ccoen 0 00 50cah clk_pck enr2 reset value pck en27 1 pck en26 1 - 1 - 1 pck en23 1 pck en22 1 - 1 - 1 00 50cbh clk_can ccr reset value - 0 - 0 - 0 - 0 - 0 candiv2 0 candiv1 0 candiv0 0 00 50cch clk_hsit rimr reset value - x - x - x - x - x hsi trim2 0 hsi trim1 0 hsi trim0 0 00 50cdh clk_swi mccr reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 swi mclk 0 table 17. clk register map and reset values (continued) address register name 76543210
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 43/120 7.2.6 interrupt controller interrupt software priority registers external interrupt control register table 18. interrupt software priority registers map address register name 76543210 00 7f70h itc_spr1 reset value vect3s pr1 1 vect3s pr0 1 vect2s pr1 1 vect2s pr0 1 vect1s pr1 1 vect1s pr0 1 reserved 1 reserved 1 00 7f71h itc_spr2 reset value vect7s pr1 1 vect7s pr0 1 vect6s pr1 1 vect6s pr0 1 vect5s pr1 1 vect5s pr0 1 vect4s pr1 1 vect4s pr0 1 00 7f72h itc_spr3 reset value vect11 spr1 1 vect11 spr0 1 vect10 spr1 1 vect10 spr0 1 vect9s pr1 1 vect9s pr0 1 vect8s pr1 1 vect8s pr0 1 00 7f73h itc_spr4 reset value vect15 spr1 1 vect15 spr0 1 vect14 spr1 1 vect14 spr0 1 vect13 spr1 1 vect13 spr0 1 vect12 spr1 1 vect12 spr0 1 00 7f74h itc_spr5 reset value vect19 spr1 1 vect19 spr0 1 vect18 spr1 1 vect18 spr0 1 vect17 spr1 1 vect17 spr0 1 vect16 spr1 1 vect16 spr0 1 00 7f75h itc_spr6 reset value vect23 spr1 1 vect23 spr0 1 vect22 spr1 1 vect22 spr0 1 vect21 spr1 1 vect21 spr0 1 vect20 spr1 1 vect20 spr0 1 00 7f76h itc_spr7 reset value reserved 1 reserved 1 reserved 1 reserved 1 reserved 1 reserved 1 vect24 spr1 1 vect24 spr0 1 table 19. external interrupt control register map address register name 7 6 5 4 3 210 00 50a0h exti_cr1 reset value pdis1 0 pdis0 0 pcis1 0 pcis0 0 pbis1 0 pbis0 0 pa i s 1 0 pa i s 0 0 00 50a1h exti_cr2 reset value reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 tlis 0 peis1 0 peis0 0
memory and register map stm8af52/62xx, stm8af51/61xx 44/120 doc id 14395 rev 7 7.2.7 timers window watchdog timer independent watchdog timer auto-wakeup counter and beeper table 20. wwdg register map and reset values address register name 76543210 00 50d1h wwdg_cr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 00 50d2h wwdg_wr reset value - 0 w6 1 w5 1 w4 1 w3 1 w2 1 w1 1 w0 1 table 21. iwdg register map address register name 76543210 00 50e0h iwdg_kr reset value key7 x key6 x key5 x key4 x key3 x key2 x key1 x key0 x 00 50e1h iwdg_pr reset value - 0 - 0 - 0 - 0 - 0 pr2 0 pr1 0 pr0 0 00 50e2h iwdg_rlr reset value rl7 1 rl6 1 rl5 1 rl4 1 rl3 1 rl2 1 rl1 1 rl0 1 table 22. awu register map address register name 76543210 00 50f0h awu_csr reset value - 0 - 0 awuf 0 awuen 0 - 0 - 0 - 0 msr 0 00 50f1h awu_apr reset value - 0 - 0 apr5 1 apr4 1 apr3 1 apr2 1 apr1 1 apr0 1 00 50f2h awu_tbr reset value - 0 - 0 - 0 - 0 awutb3 0 awutb2 0 awutb1 0 awutb0 0 table 23. beep register map address register name 7 6543210 00 50f3h beep_csr reset value beep sel2 0 beep sel1 0 beep en 0 beep div4 0 beep div3 0 beep div2 0 beep div1 0 beep div0 0
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 45/120 tim1 table 24. tim1 register map address register name 7 6 5 4 3 2 1 0 00 5250h tim1_cr1 reset value arpe 0 cms1 0 cms0 0 dir 0 opm 0 urs 0 udis 0 cen 0 00 5251h tim1_cr2 reset value ti1s 0 mms2 0 mms1 0 mms0 0 - 0 coms 0 - 0 ccpc 0 00 5252h tim1_smcr reset value msm 0 ts2 0 ts1 0 ts0 0 - 0 sms2 0 sms1 0 sms0 0 00 5253h tim1_etr reset value etp 0 ece 0 etps1 0 etps0 0 eft3 0 eft2 0 eft1 0 eft0 0 00 5254h tim1_ier reset value bie 0 tie 0 comie 0 cc4ie 0 cc3ie 0 cc2ie 0 cc1ie 0 uie 0 00 5255h tim1_sr1 reset value bif 0 tif 0 comif 0 cc4if 0 cc3if 0 cc2if 0 cc1if 0 uif 0 00 5256h tim1_sr2 reset value - 0 - 0 - 0 cc4of 0 cc3of 0 cc2of 0 cc1of 0 - 0 00 5257h tim1_egr reset value bg 0 tg 0 comg 0 cc4g 0 cc3g 0 cc2g 0 cc1g 0 ug 0 00 5258h tim1_ccmr1 (output mode) reset value oc1ce 0 oc1m2 0 oc1m1 0 oc1m0 0 oc1pe 0 oc1fe 0 cc1s1 0 cc1s0 0 tim1_ccmr1 (input mode) reset value ic1f3 0 ic1f2 0 ic1f1 0 ic1f0 0 ic1psc1 0 ic1psc0 0 cc1s1 0 cc1s0 0 00 5259h tim1_ ccmr2 (output mode) reset value oc2ce 0 oc2m2 0 oc2m1 0 oc2m0 0 oc2pe 0 oc2fe 0 cc2s1 0 cc2s0 0 tim1_ccmr2 (input mode) reset value ic2f3 0 ic2f2 0 ic2f1 0 ic2f0 0 ic2psc1 0 ic2psc0 0 cc2s1 0 cc2s0 0 00 525ah tim1_ccmr3 (output mode) reset value oc3ce 0 oc3m2 0 oc3m1 0 oc3m0 0 oc3pe 0 oc3fe 0 cc3s1 0 cc3s0 0 tim1_ccmr3 (input mode) reset value ic3f3 0 ic3f2 0 ic3f1 0 ic3f0 0 ic3psc1 0 ic3psc0 0 cc3s1 0 cc3s0 0
memory and register map stm8af52/62xx, stm8af51/61xx 46/120 doc id 14395 rev 7 00 525bh tim1_ccmr4 (output mode) reset value oc4ce 0 oc4m2 0 oc4m1 0 oc4m0 0 oc4pe 0 oc4fe 0 cc4s1 0 cc4s0 0 tim1_ccmr4 (input mode) reset value ic4f3 0 ic4f2 0 ic4f1 0 ic4f0 0 ic4psc1 0 ic4psc0 0 cc4s1 0 cc4s0 0 00 525ch tim1_ccer1 reset value cc2np 0 cc2ne 0 cc2p 0 cc2e 0 cc1np 0 cc1ne 0 cc1p 0 cc1e 0 00 525dh tim1_ccer2 reset value - 0 - 0 cc4p 0 cc4e 0 cc3np 0 cc3ne 0 cc3p 0 cc3e 0 00 525eh tim1_cntrh reset value cnt15 0 cnt14 0 cnt13 0 cnt12 0 cnt11 0 cnt10 0 cnt9 0 cnt8 0 00 525fh tim1_cntrl reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 00 5260h tim1_pscrh reset value psc15 0 psc14 0 psc13 0 psc12 0 psc11 0 psc10 0 psc9 0 psc8 0 00 5261h tim1_pscrl reset value psc7 0 psc6 0 psc5 0 psc4 0 psc3 0 psc2 0 psc1 0 psc0 0 00 5262h tim1_arrh reset value arr15 1 arr14 1 arr13 1 arr12 1 arr11 1 arr10 1 arr9 1 arr8 1 00 5263h tim1_arrl reset value arr7 1 arr6 1 arr5 1 arr4 1 arr3 1 arr2 1 arr1 1 arr0 1 00 5264h tim1_rcr reset value rep7 0 rep6 0 rep5 0 rep4 0 rep3 0 rep2 0 rep1 0 rep0 0 00 5265h tim1_ccr1h reset value ccr115 0 ccr114 0 ccr113 0 ccr112 0 ccr111 0 ccr110 0 ccr19 0 ccr18 0 00 5266h tim1_ccr1l reset value ccr17 0 ccr16 0 ccr15 0 ccr14 0 ccr13 0 ccr12 0 ccr11 0 ccr10 0 00 5267h tim1_ccr2h reset value ccr215 0 ccr214 0 ccr213 0 ccr212 0 ccr211 0 ccr210 0 ccr29 0 ccr28 0 00 5268h tim1_ccr2l reset value ccr27 0 ccr26 0 ccr25 0 ccr24 0 ccr23 0 ccr22 0 ccr21 0 ccr20 0 00 5269h tim1_ccr3h reset value ccr315 0 ccr314 0 ccr313 0 ccr312 0 ccr311 0 ccr310 0 ccr39 0 ccr38 0 00 526ah tim1_ccr3l reset value ccr37 0 ccr36 0 ccr35 0 ccr34 0 ccr33 0 ccr32 0 ccr31 0 ccr3 0 0 00 526bh tim1_ccr4h reset value ccr415 0 ccr414 0 ccr413 0 ccr412 0 ccr411 0 ccr410 0 ccr49 0 ccr48 0 00 526ch tim1_ccr4l reset value ccr47 0 ccr46 0 ccr45 0 ccr44 0 ccr43 0 ccr42 0 ccr41 0 ccr40 0 table 24. tim1 register map (continued) address register name 7 6 5 4 3 2 1 0
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 47/120 tim2 00 526dh tim1_bkr reset value moe 0 aoe 0 bkp 0 bke 0 ossr 0 ossi 0 lock 0 lock 0 00 526eh tim1_dtr reset value dtg7 0 dtg6 0 dtg5 0 dtg4 0 dtg3 0 dtg2 0 dtg1 0 dtg0 0 00 526fh tim1_oisr reset value - 0 ois4 0 ois3n 0 ois3 0 ois2n 0 ois2 0 ois1n 0 ois1 0 table 24. tim1 register map (continued) address register name 7 6 5 4 3 2 1 0 table 25. tim2 register map address register name 7 6 5 4 3 2 1 0 00 5300h tim2_cr1 reset value arpe 0 - 0 - 0 - 0 opm 0 urs 0 udis 0 cen 0 00 5301h tim2_ier reset value - 0 - 0 - 0 - 0 cc3ie 0 cc2ie 0 cc1ie 0 uie 0 00 5302h tim2_sr1 reset value - 0 - 0 - 0 - 0 cc3if 0 cc2if 0 cc1if 0 uif 0 00 5303h tim2_sr2 reset value - 0 - 0 - 0 - 0 cc3of 0 cc2of 0 cc1of 0 - 0 00 5304h tim2_egr reset value - 0 - 0 - 0 - 0 cc3g 0 cc2g 0 cc1g 0 ug 0 00 5305h tim2_ccmr1 (output mode) reset value - 0 oc1m2 0 oc1m1 0 oc1m0 0 oc1pe 0 - 0 cc1s1 0 cc1s0 0 tim2_ccmr1 (input mode) reset value ic1f3 0 ic1f2 0 ic1f1 0 ic1f0 0 ic1psc1 0 ic1psc0 0 cc1s1 0 cc1s0 0 00 5306h tim2_ ccmr2 (output mode) reset value - 0 oc2m2 0 oc2m1 0 oc2m0 0 oc2pe 0 - 0 cc2s1 0 cc2s0 0 tim2_ccmr2 (input mode) reset value ic2f3 0 ic2f2 0 ic2f1 0 ic2f0 0 ic2psc1 0 ic2psc0 0 cc2s1 0 cc2s0 0 00 5307h tim2_ccmr3 (output mode) reset value - 0 oc3m2 0 oc3m1 0 oc3m0 0 oc3pe 0 - 0 cc3s1 0 cc3s0 0 tim2_ccmr3 (input mode) reset value ic3f3 0 ic3f2 0 ic3f1 0 ic3f0 0 ic3psc1 0 ic3psc0 0 cc3s1 0 cc3s0 0
memory and register map stm8af52/62xx, stm8af51/61xx 48/120 doc id 14395 rev 7 tim3 00 5308h tim2_ccer1 reset value - 0 - 0 cc2p 0 cc2e 0 - 0 - 0 cc1p 0 cc1e 0 00 5309h tim2_ccer2 reset value - 0 - 0 - 0 - 0 - 0 - 0 cc3p 0 cc3e 0 00 530ah tim2_cntrh reset value cnt15 0 cnt14 0 cnt13 0 cnt12 0 cnt11 0 cnt10 0 cnt9 0 cnt8 0 00 530bh tim2_cntrl reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 00 530ch tim2_pscr reset value - 0 - 0 - 0 - 0 psc3 0 psc2 0 psc1 0 psc0 0 00 530dh tim2_arrh reset value arr15 1 arr14 1 arr13 1 arr12 1 arr11 1 arr10 1 arr9 1 arr8 1 00 530eh tim2_arrl reset value arr7 1 arr6 1 arr5 1 arr4 1 arr3 1 arr2 1 arr1 1 arr0 1 00 530fh tim2_ccr1h reset value ccr115 0 ccr114 0 ccr113 0 ccr112 0 ccr111 0 ccr110 0 ccr19 0 ccr18 0 00 5310h tim2_ccr1l reset value ccr17 0 ccr16 0 ccr15 0 ccr14 0 ccr13 0 ccr12 0 ccr11 0 ccr10 0 00 5311h tim2_ccr2h reset value ccr215 0 ccr214 0 ccr213 0 ccr212 0 ccr211 0 ccr210 0 ccr29 0 ccr28 0 00 5312h tim2_ccr2l reset value ccr27 0 ccr26 0 ccr25 0 ccr24 0 ccr23 0 ccr22 0 ccr21 0 ccr20 0 00 5313h tim2_ccr3h reset value ccr315 0 ccr314 0 ccr313 0 ccr312 0 ccr311 0 ccr310 0 ccr39 0 ccr38 0 00 5314h tim2_ccr3l reset value ccr37 0 ccr36 0 ccr35 0 ccr34 0 ccr33 0 ccr32 0 ccr31 0 ccr30 0 table 25. tim2 register map (continued) address register name 7 6 5 4 3 2 1 0 table 26. tim3 register map addressregister name7654 3 2 10 00 5320h tim3_cr1 reset value arpe 0 - 0 - 0 - 0 opm 0 urs 0 udis 0 cen 0 00 5321h tim3_ier reset value - 0 - 0 - 0 - 0 - 0 cc2ie 0 cc1ie 0 uie 0 00 5322h tim3_sr1 reset value - 0 - 0 - 0 - 0 - 0 cc2if 0 cc1if 0 uif 0 00 5323h tim3_sr2 reset value - 0 - 0 - 0 - 0 - 0 cc2of 0 cc1of 0 - 0
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 49/120 00 5324h tim3_egr reset value - 0 - 0 - 0 - 0 - 0 cc2g 0 cc1g 0 ug 0 00 5325h tim3_ccmr1 (output mode) reset value - 0 oc1m2 0 oc1m1 0 oc1m0 0 oc1pe 0 - 0 cc1s1 0 cc1s0 0 tim3_ccmr1 (input mode) reset value ic1f3 0 ic1f2 0 ic1f1 0 ic1f0 0 ic1psc1 0 ic1psc0 0 cc1s1 0 cc1s0 0 00 5326h tim3_ ccmr2 (output mode) reset value - 0 oc2m2 0 oc2m1 0 oc2m0 0 oc2pe 0 - 0 cc2s1 0 cc2s0 0 tim3_ccmr2 (input mode) reset value ic2f3 0 ic2f2 0 ic2f1 0 ic2f0 0 ic2psc1 0 ic2psc0 0 cc2s1 0 cc2s0 0 00 5327h tim3_ccer1 reset value - 0 - 0 cc2p 0 cc2e 0 - 0 - 0 cc1p 0 cc1e 0 00 5328h tim3_cntrh reset value cnt15 0 cnt14 0 cnt13 0 cnt12 0 cnt11 0 cnt10 0 cnt9 0 cnt8 0 00 5329h tim3_cntrl reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 00 532ah tim3_pscr reset value - 0 - 0 - 0 - 0 psc3 0 psc2 0 psc1 0 psc0 0 00 532bh tim3_arrh reset value arr15 1 arr14 1 arr13 1 arr12 1 arr11 1 arr10 1 arr9 1 arr8 1 00 532ch tim3_arrl reset value arr7 1 arr6 1 arr5 1 arr4 1 arr3 1 arr2 1 arr1 1 arr0 1 00 532dh tim3_ccr1h reset value ccr115 0 ccr114 0 ccr113 0 ccr112 0 ccr111 0 ccr110 0 ccr19 0 ccr18 0 00 532eh tim3_ccr1l reset value ccr17 0 ccr16 0 ccr15 0 ccr14 0 ccr13 0 ccr12 0 ccr11 0 ccr10 0 00 532fh tim3_ccr2h reset value ccr215 0 ccr214 0 ccr213 0 ccr212 0 ccr211 0 ccr210 0 ccr29 0 ccr28 0 00 5330h tim3_ccr2l reset value ccr27 0 ccr26 0 ccr25 0 ccr24 0 ccr23 0 ccr22 0 ccr21 0 ccr20 0 table 26. tim3 register map (continued) addressregister name7654 3 2 10
memory and register map stm8af52/62xx, stm8af51/61xx 50/120 doc id 14395 rev 7 tim4 7.2.8 communication interfaces serial peripheral interface (spi) table 27. tim4 register map addressregister name76543210 00 5340h tim4_cr1 reset value arpe 0 - 0 - 0 - 0 opm 0 urs 0 udis 0 cen 0 00 5341h tim4_ier reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 uie 0 00 5342h tim4_sr1 reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 uif 0 00 5343h tim4_egr reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 ug 0 00 5344h tim4_cntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 00 5345h tim4_pscr reset value - 0 - 0 - 0 - 0 - 0 psc2 0 psc1 0 psc0 0 00 5346h tim4_arr reset value arr7 1 arr6 1 arr5 1 arr4 1 arr3 1 arr2 1 arr1 1 arr0 1 table 28. spi register map and reset value address register name 7654 3210 00 5200h spi_cr1 reset value lsbfirst 0 spe 0 br2 0 br1 0 br1 0 mstr 0 cpol 0 cpha 0 00 5201h spi_cr2 reset value bdm 0 bdoe 0 crcen 0 crcnext 0 reserved 0 rxonly 0 ssm 0 ssi 0 00 5202h spi_icr reset value txie 0 rxie 0 errie 0 wkie 0 reserved 0 reserved 0 reserved 0 reserved 0 00 5203h spi_sr reset value bsy 0 ovr 0 modf 0 crcerr 0 wkup 0 reserved 0 txe 1 rxne 0 00 5204h spi_dr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 00 5205h spi_crcpr reset value msb 0 - 0 - 0 - 0 - 0 - 1 - 1 lsb 1
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 51/120 inter integrated circuit (i 2 c) interface 00 5206h spi_ rxcrcr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 00 5207h spi_ txcrcr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 table 28. spi register map and reset value (continued) address register name 7654 3210 table 29. i 2 c register map address register name 7 6 5 4 3 2 1 0 00 5210h i2c_cr1 reset value no stretch 0 engc 0 - 0 - 0 - 0 - 0 - 0 pe 0 00 5211h i2c_cr2 reset value swrst 0 - 0 - 0 - 0 pos 0 ack 0 stop 0 start 0 00 5212h i2c_ freqr reset value - 0 - 0 freq5 0 freq4 0 freq3 0 freq2 0 freq1 0 freq0 0 00 5213h i2c_oarl reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 00 5214h i2c_oarh reset value add mode 0 add conf 0 - 0 - 0 - 0 add9 0 add8 0 - 0 00 5215h reserved 00 5216h i2c_dr reset value dr7 0 dr6 0 dr5 0 dr4 0 dr3 0 dr2 0 dr1 0 dr0 0 00 5217h i2c_sr1 reset value txe 0 rxne 0 - 0 stopf 0 add10 0 btf 0 addr 0 sb 0 00 5218h i2c_sr2 reset value - 0 - 0 wufh 0 - 0 ovr 0 af 0 arlo 0 berr 0
memory and register map stm8af52/62xx, stm8af51/61xx 52/120 doc id 14395 rev 7 universal synchronous/asynchronous receiver transmitter (usart) 00 5219h i2c_sr3 reset value - 0 - 0 - 0 gen call 0 - 0 tra 0 busy 0 msl 0 00 521ah i2c_itr reset value - 0 - 0 - 0 - 0 - 0 itbufen 0 itevten 0 iterren 0 00 521bh i2c_ccrl reset value ccr7 0 ccr6 0 ccr5 0 ccr4 0 ccr3 0 ccr2 0 ccr1 0 ccr0 0 00 521ch i2c_ccrh reset value fs 0 duty 0 - 0 - 0 ccr11 0 ccr10 0 ccr9 0 ccr8 0 00 521dh i2c_ triser reset value - 0 - 0 trise5 0 trise4 0 trise3 0 trise2 0 trise1 1 trise0 0 table 29. i 2 c register map (continued) address register name 7 6 5 4 3 2 1 0 table 30. usart register map address register name 7 6 5 4 3 2 1 0 00 5230h usart_sr reset value txe 1 tc 1 rxne 0 idle 0 or 0 nf 0 fe 0 pe 0 00 5231h usart_dr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 00 5232h usart_brr1 reset value usart_div[11:4] 00000000 00 5233h usart_brr2 reset value usart_div[15:12] 0000 usart_div[3:0] 0000 00 5234h usart_cr1 reset value r8 0 t8 0 usartd 0 m 0 - 0 pcen 0 ps 0 pien 0 00 5235h usart_cr2 reset value tien 0 tcien 0 rien 0 ilien 0 ten 0 ren 0 rwu 0 sbk 0 00 5236h usart_cr3 reset value - 0 linen 0 stop 00 cken 0 cpol 0 cpha 0 lbcl 0 00 5237h usart_cr4 reset value - 0 lbdien 0 lbdl 0 lbdf 0 - 0 - 0 - 0 - 0
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 53/120 universal asynchronous receiver/transmitter with lin support (linuart) table 31. linuart register map and reset value address register name 7 6 5 4 3 2 1 0 00 5240h linuart_sr reset value txe 1 tc 1 rxne 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 005241h linuart_dr reset value dr7 0 dr6 0 dr5 0 dr4 0 dr3 0 dr2 0 dr1 0 dr0 0 00 5242h linuart_brr1 reset value ldiv[11:8] 00000000 00 5243h linuart_brr2 reset value ldiv[15:12] 0000 ldiv[3:0] 0000 00 5244h linuart_cr1 reset value r8 0 t8 0 uartd 0 m 0 wake 0 pcen 0 ps 0 pien 0 00 5245h linuart_cr2 reset value tien 0 tcien 0 rien 0 ilien 0 ten 0 ren 0 rwu 0 sbk 0 00 5246h linuart_cr3 reset value - 0 linen 0 stop 00 - 0 - 0 - 0 - 0 00 5247h linuart_cr4 reset value - 0 lbdien 0 lbdl 0 lbdf 0 add[3:0] 0000 00 5248h reserved 00 5249h linuart_cr6 reset value ldum 0 - 0 lslv 0 lase 0 - 0 lhdien 0 lhdf 0 lsf 0
memory and register map stm8af52/62xx, stm8af51/61xx 54/120 doc id 14395 rev 7 can figure 8. can regi ster mapping 5420h 5421h can master control register can master status register can transmit status register can transmit priority register can_mcr can_msr can_tsr can_tpr can receive fifo register can_rfr can interrupt enable register can diagnostic register can_ier can_dgr can page selection register can_psr 5422h 5423h 5424h 5425h 5426h 5427h xxh paged register 0 paged register 1 paged register 2 paged register 3 paged register 4 paged register 5 paged register 6 paged register 7 paged register 8 paged register 9 paged register 10 paged register 11 paged register 12 paged register 13 paged register 14 paged register 15
stm8af52/62xx, stm8af51/61xx memory and register map doc id 14395 rev 7 55/120 figure 9. can page mapping 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh page 0 page 1 page 2 page 3 tx mailbox 0 tx mailbox 1 acceptance filter 0:1 acceptance filter 2:3 can_mcsr can_mdlcr can_mtsrl can_mtsrh can_midr1 can_midr2 can_midr3 can_midr4 can_mdar1 can_mdar2 can_mdar3 can_mdar4 can_mdar5 can_mdar6 can_mdar7 can_mdar8 can_mcsr can_mdlcr can_mtsrl can_mtsrh can_midr1 can_midr2 can_midr3 can_midr4 can_mdar1 can_mdar5 can_mdar6 can_mdar4 can_mdar5 can_mdar6 can_mdar7 can_mdar8 can_f0r1 can_f0r2 can_f0r3 can_f0r4 can_f0r5 can_f0r6 can_f0r7 can_f0r8 can_f1r1 can_f1r2 can_f1r3 can_f1r4 can_f1r5 can_f1r6 can_f1r7 can_f1r8 can_f2r1 can_f2r2 can_f2r3 can_f2r4 can_f2r5 can_f2r6 can_f2r7 can_f2r8 can_f3r1 can_f3r2 can_f3r3 can_f3r4 can_f3r5 can_f3r6 can_f3r7 can_f3r8 can_mfmir can_mdlcr can_mtsrl can_mtsrh page 7 receive fifo can_midr1 can_midr2 can_midr3 can_midr4 can_mdar1 can_mdar2 can_mdar3 can_mdar4 can_mdar5 can_mdar6 can_mdar7 can_mdar8 page 6 configuration/diagnostic can_esr can_eier reserved reserved can_tecr can_recr can_btr1 can_btr2 reserved reserved can_fmr1 can_fmr2 can_fcr1 can_fcr2 can_fcr3 reserved page 4 acceptance filter 4:5 can_f4r1 can_f4r2 can_f4r3 can_f4r4 can_f4r5 can_f4r6 can_f4r7 can_f4r8 can_f5r1 can_f5r2 can_f5r3 can_f5r4 can_f5r5 can_f5r6 can_f5r7 can_f5r8 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh page 5 tx mailbox 2 can_mcsr can_mdlcr can_mtsrl can_mtsrh can_midr1 can_midr2 can_midr3 can_midr4 can_mdar1 can_mdar2 can_mdar3 can_mdar4 can_mdar5 can_mdar6 can_mdar7 can_mdar8 (if txm2e = 1 in can_dgr register)
memory and register map stm8af52/62xx, stm8af51/61xx 56/120 doc id 14395 rev 7 7.3 analog to digital converter (adc) table 32. adc register map and reset value address register name 7 6 5 4 3 2 1 0 00 5400h adc _csr reset value eoc 0 - 0 eocie 0 - 0 ch3 0 ch2 0 ch1 0 ch0 0 00 5401h adc_cr1 reset value - 0 spsel2 0 spsel1 0 spsel0 0 - 0 - 0 cont 0 adon 0 00 5402h adc_cr2 reset value - 0 exttrig 0 extsel1 0 extsel0 0 align 0 - 0 - 0 - 0 00 5403h reserved 00 5404h adc_drh1 reset value data9 0 data8 0 data7 0 data6 0 data5 0 data4 0 data3 0 data2 0 00 5405h adc_drl1 reset value - 0 - 0 - 0 - 0 - 0 - 0 data1 0 data0 0 00 5406h adc_tdrh reset value td15 0 td14 0 td13 0 td12 0 td11 0 td10 0 td9 0 td8 0 00 5407h adc_tdrl reset value td7 0 td6 0 td5 0 td4 0 td3 0 td2 0 td1 0 td0 0
stm8af52/62xx, stm8af51/61xx interrupt table doc id 14395 rev 7 57/120 8 interrupt table table 33. stm8a interrupt table (1) priority source block description interrupt vector address wakeup from halt comments ? reset reset 6000h yes reset vector in rom ? trap sw interrupt 8004h ? ? 0tli external top level interrupt 8008h ? ? 1awu auto-wakeup from halt 800ch yes ? 2 clock controller main clock controller 8010h ? ? 3 misc external interrupt e0 8014h yes port a interrupts 4 misc external interrupt e1 8018h yes port b interrupts 5 misc external interrupt e2 801ch yes port c interrupts 6 misc external interrupt e3 8020h yes port d interrupts 7 misc external interrupt e4 8024h yes port e interrupts 8 can can interrupt rx 8028h yes ? 9can can interrupt tx/er/sc 802ch ? ? 10 spi end of transfer 8030h yes ? 11 timer 1 update/overflow/ trigger/break 8034h ? ? 12 timer 1 capture/compare 8038h ? ? 13 timer 2 update/overflow 803ch ? ? 14 timer 2 capture/compare 8040h ? ? 15 timer 3 update/overflow 8044h ? ? 16 timer 3 capture/compare 8048h ? ? 17 usart (sci1) tx complete 804ch ? ? 18 usart (sci1) receive data full reg. 8050h ? ? 19 i 2 c i 2 c interrupts 8054h yes ? 20 linuart (sci2) tx complete/error 8058h ? ? 21 linuart (sci2) receive data full reg. 805ch ? ? 22 adc end of conversion 8060h ? ?
interrupt table stm8af52/62xx, stm8af51/61xx 58/120 doc id 14395 rev 7 23 timer 4 update/overflow 8064h ? ? 24 eeprom end of programming/ write in not allowed area 8068h ? ? 1. all unused interrupts must be initializ ed with ?iret? for robust programming. table 33. stm8a interrupt table (1) (continued) priority source block description interrupt vector address wakeup from halt comments
stm8af52/62xx, stm8af51/61xx option bytes doc id 14395 rev 7 59/120 9 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. each option byte has to be stored twice, for redundancy, in a regular form (optx) and a complemented one (noptx), except for the rop (read-out protection) option byte and option bytes 8 to 16. option bytes can be modified in icp mode (v ia swim) by accessing the eeprom address shown in table 34: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be changed in icp mode (via swim). refer to the stm8 flash programming manual (pm0047) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures.
option bytes stm8af52/62xx, stm8af51/61xx 60/120 doc id 14395 rev 7 table 34. option bytes addr. option name option byte no. option bits factory default setting 76543 2 1 0 4800h read-out protection (rop) opt0 rop[7:0] 00h 4801h user boot code (ubc) opt1 ubc[7:0] 00h 4802h nopt1 nubc[7:0] ffh 4803h alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 00h 4804h nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 ffh 4805h watchdog option opt3 reserved lsi_ en iwdg _hw wwd g _hw wwdg _halt 00h 4806h nopt3 reserved nlsi_ en niwd g_hw nwwd g_hw nwwg _halt ffh 4807h clock option opt4 reserved ext clk ckaw usel prsc1 prsc0 00h 4808h nopt4 reserved next clk nckaw usel nprsc1 nprsc 0 ffh 4809h hse clock startup opt5 hsecnt[7:0] 00h 480ah nopt5 nhsecnt[7:0] ffh 480bh tmu opt6 tmu[3:0] 00h 480ch nopt6 ntmu[3:0] ffh 480dh flash wait states opt7 reserved wait state 00h 480eh nopt7 reserved nwait state ffh 480fh reserved 4810h tmu opt8 tmu_key 1 [7:0] 00h 4811h opt9 tmu_key 2 [7:0] 00h 4812h opt10 tmu_key 3 [7:0] 00h 4813h opt11 tmu_key 4 [7:0] 00h 4814h opt12 tmu_key 5 [7:0] 00h 4815h opt13 tmu_key 6 [7:0] 00h 4816h opt14 tmu_key 7 [7:0] 00h 4817h opt15 tmu_key 8 [7:0] 00h 4818h opt16 tmu max_att [7:0] 00h 4819h to 487d reserved
stm8af52/62xx, stm8af51/61xx option bytes doc id 14395 rev 7 61/120 487e boot- loader (1) opt17 bl [7:0] 00h 487f nopt 17 nbl [7:0] 00h 1. this option consists of two by tes that must have a complementary value in order to be valid. if the option is invalid, it has no effect. table 34. option bytes (continued) addr. option name option byte no. option bits factory default setting 76543 2 1 0
option bytes stm8af52/62xx, stm8af51/61xx 62/120 doc id 14395 rev 7 table 35. option byte description option byte no. description opt0 rop[7:0]: memory readout protection (rop) aah: enable readout protection (w rite access via swim protocol) note: refer to the stm8a microcontroller family reference manual (rm0009) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0]: user boot code area 00h: no ubc, no write-protection 01h: page 0 to 1 defined as ubc, memory write-protected 02h: page 0 to 3 defined as ubc, memory write-protected 03h to ffh: pages 4 to 255 defined as ubc, memory write-protected note: refer to the stm8a microcontroller family reference manual (rm0009) section on flash/eeprom wr ite protection for more details. opt2 afr7: alternate function remapping option 7 0: port d4 alternate function = tim2_cc1 1: port d4 alternate function = beep afr6: alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 alternate function = i 2 c_scl. afr5: alternate function remapping option 5 0: port b3 alternate function = ai n3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0. 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ncc3, port b1 alternate func tion = tim1_ncc2, port b0 alternate function = tim1_ncc1. afr4: alternate function remapping option 4 0: port d7 alternate function = tli 1: reserved afr3: alternate function remapping option 3 0: port d0 alternate function = tim3_cc2 1: port d0 alternate function = tim1_bkin afr2: alternate function remapping option 2 0: port d0 alternate function = tim3_cc2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1: alternate function remapping option 1 0: port a3 alternate function = ti m2_cc3, port d2 alternate function tim3_cc1. 1: port a3 alternate function = ti m3_cc1, port d2 alternate function tim2_cc3. afr0: alternate function remapping option 0 0: port d3 alternate function = tim2_cc2 1: port d3 alternate function = adc_etr
stm8af52/62xx, stm8af51/61xx option bytes doc id 14395 rev 7 63/120 opt3 lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal c onnected to oscin/oscout 1: external clock signal on oscin ckawusel: auto-wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for awu prsc[1:0]: awu clock prescaler 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilization ti me to 0.5, 8, 128, and 2048 hse cycles with corresponding option byte values of e1h, d2h, b4h, and 00h. opt6 tmu[3:0]: enable temporary memory unprotection 0101: tmu disabled (permanent rop). any other value: tmu enabled. opt7 wait state: wait state configuration this option configures the number of wait states inserted when reading from the flash/data eeprom memory. 0: no wait state 1: one wait state opt8 tmu_key 1 [7:0]: temporary unprotection key 0 temporary unprotection key: must be different from 00h or ffh opt9 tmu_key 2 [7:0]: temporary unprotection key 1 temporary unprotection key: must be different from 00h or ffh opt10 tmu_key 3 [7:0]: temporary unprotection key 2 temporary unprotection key: must be different from 00h or ffh opt11 tmu_key 4 [7:0]: temporary unprotection key 3 temporary unprotection key: must be different from 00h or ffh table 35. option byte description (continued) option byte no. description
option bytes stm8af52/62xx, stm8af51/61xx 64/120 doc id 14395 rev 7 opt12 tmu_key 5 [7:0]: temporary unprotection key 4 temporary unprotection key: must be different from 00h or ffh opt13 tmu_key 6 [7:0]: temporary unprotection key 5 temporary unprotection key: must be different from 00h or ffh opt14 tmu_key 7 [7:0]: temporary unprotection key 6 temporary unprotection key: must be different from 00h or ffh opt15 tmu_key 8 [7:0]: temporary unprotection key 7 temporary unprotection key: must be different from 00h or ffh opt16 tmu_maxatt [7:0]: tmu access failure counter every unsuccessful trial to enter t he temporary unprotection procedure increments the counter. more than ei ght unsuccessful trials trigger the global erase of the code and data memory. opt17 bl[7:0]: bootloader enable if this option byte is set to 55h (complementary value aah) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, um0500). table 35. option byte description (continued) option byte no. description
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 65/120 10 electrical characteristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 10.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = -40 c, t a = 25 c, and t a = t amax (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range . 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . figure 10. pin loading conditions 50 pf stm8a pin
electrical characteristics stm8af52/62xx, stm8af51/61xx 66/120 doc id 14395 rev 7 10.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 11. pin input voltage 10.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8a pin table 36. voltage characteristics symbol ratings min max unit v ddx - v dd supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection current, and the corresponding v in maximum must always be respected v ss - 0.3 6.5 v input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v dd | variations between different power pins ? 50 mv |v ssx - v ss | variations between all the different ground pins ? 50 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 94
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 67/120 table 37. current characteristics symbol ratings max. unit i vddio total current into v ddio power lines (source) (1)(2)(3) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 2. the total limit applies to the sum of operation and injected currents. 3. v ddio includes the sum of the positive injection currents. v ssio includes the sum of the negative injection currents. 100 ma i vssio total current out of v ss io ground lines (sink) (1)(2)(3) 100 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin -20 i inj(pin) (4) 4. this condition is im plicitly insured if vin maximum is respec ted. if vin maximum cannot be respected, the injection current must be limited externally to the iin j(pin) value. a positive injection is induced by vin > vdd while a negative injection is induced by vin < vss. for true open-drain pads , there is no positive injection current allowed and the correspondi ng vin maximum must always be respected. injected current on any pin 10 i inj(tot) sum of injected currents 50 table 38. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to 150 c t j maximum junction temperature 160 table 39. operating lifetime (1) 1. for detailed mission profile analysis, plea se contact your local st sales office. symbol ratings value unit olf conforming to aec-q100 rev g ? 40 to 125 c grade 1 ? 40 to 150 c grade 0
electrical characteristics stm8af52/62xx, stm8af51/61xx 68/120 doc id 14395 rev 7 10.3 operating conditions figure 12. f cpumax versus v dd 1. for devices with less than 96 kbyte of program me mory, the 24 mhz are only ac hievable using the super set silicon (salestype contains sss) table 40. general operating conditions symbol parameter conditions min max unit f cpu internal cpu clock frequency 1 wait state t a = -40 c to 150 c 16 24 (1) 1. for devices with less than 96 kbyte of program me mory, the 24 mhz are only ac hievable using the super set silicon (salestype contains sss) mhz 0 wait state t a = -40 c to 150 c 016 v dd/ v ddio standard operating voltage - 3.0 5.5 v v cap c ext capacitance of external capacitor (2) 2. this parameter range must be respected for the full application range, taking in to account the physical capacitor characteristics and tolerance. 470 3300 nf esr of external capacitor (2) at 1 mhz 0.3 esl of external capacitor (2) 15 nh t a ambient temperature suffix a -40 85 c suffix b 105 suffix c 125 suffix d 150 t j junction temperature range suffix a 90 suffix b 110 suffix c 130 suffix d 155 f cpu [mhz] supply voltage [v] 24 12 8 4 0 3.0 4.0 5.0 functionality not guaranteed in this area 16 5.5 functionality guaranteed @ t a -40 to 150 c at 1 waitstate (1) functionality guaranteed @ t a -40 to 150 c at 0 waitstate
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 69/120 10.3.1 vcap external capacitor stabilization for the ma in regulator is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in ta b l e 4 0 . care should be taken to limit the series inductance to less than 15 nh. figure 13. external capacitor c ext 1. legend: esr is the equivalent series resi stance and esl is the equivalent inductance. 10.3.2 supply current characteristics the current consumption is measured as described in figure 10 on page 65 and figure 11 on page 66 . if not explicitly stated, general conditions of temperature and voltage apply. table 41. operating conditions at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate ? 2 (1) 1. guaranteed by design, not tested in production. ? 8 s/v v dd fall time rate ? 2 (1) ? 8 t temp reset release delay v dd rising ? 3 ? ms reset generation delay v dd falling ? 3 ? s v it+ power-on reset threshold (2) 2. if v dd is below 3 v, the code execution is guaranteed above the v it- and v it+ thresholds. ram content is kept. the eeprom programming sequence must not be initiated. ? 2.65 2.8 2.95 v v it- brown-out reset threshold ? 2.58 2.73 2.88 v hys(bor) brown-out reset hysteresis ??70 (1) mv c rleak esr esl
electrical characteristics stm8af52/62xx, stm8af51/61xx 70/120 doc id 14395 rev 7 table 42. total current consumption in run, wait and slow mode. general conditions for v dd apply. t a = -40 c to 150 c symbol parameter conditions typ max unit i dd(run) (1) supply current in run mode all peripherals clocked, code executed from eeprom, hse external clock f cpu = 24 mhz 1 ws 8.7 16.8 (2)(3) ma f cpu = 16 mhz 7.4 14 f cpu = 8 mhz 4.0 7.4 (2) f cpu = 4 mhz 2.4 4.1 (2) f cpu = 2 mhz 1.5 2.5 i dd(run) (1) supply current in run mode all peripherals clocked, code executed from ram, hse external clock f cpu = 24 mhz 4.4 6.0 (2)(3) f cpu = 16 mhz 3.7 5.0 f cpu = 8 mhz 2.2 3.0 (2) f cpu = 4 mhz 1.4 2.0 (2) f cpu = 2 mhz 1.0 1.5 i dd(wfi) (1) supply current in wait mode cpu stopped, all peripherals off, hse external clock f cpu = 24 mhz 2.4 3.1 (2)(3) f cpu = 16 mhz 1.65 2.5 f cpu = 8 mhz 1.15 1.9 (2) f cpu = 4 mhz 0.90 1.6 (2) f cpu = 2 mhz 0.80 1.5 i dd(slow) (1) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram external clock 16 mhz f cpu = 125 khz 1.50 1.95 lsi internal rc f cpu = 128 khz 1.50 1.80 (2) 1. the current due to i/o utilization is not taken into account in these values. 2. values not tested in production. design guidelines only. 3. for devices with less than 96 kbyte of program memory, the 24 mhz are only achievable using the super set silicon (salestype contains sss)
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 71/120 current consumption for on-chip peripherals table 43. total current consumption in halt and active halt modes. general conditions for v dd apply. t a = -40 c to 55 c unless otherwise stated symbol parameter conditions typ max unit i dd(h) supply current in halt mode clocks stopped, flash in power-down mode 535 (1) a clocks stopped, flash in power-down mode, t a = 25 c 525 i dd(fah) supply current in fast active halt mode external clock 16 mhz f master = 125 khz 770 900 (1) lsi clock 128 khz 150 230 (1) i dd(sah) supply current in slow active halt mode lsi clock 128 khz 25 42 (1) lsi clock 128 khz, t a = 25 c 25 30 t wu(fah) wakeup time from fast active halt mode t a = -40 c to 150 c 10 30 (1) s t wu(sah) wakeup time from slow active halt mode 50 80 (1) 1. data based on characterization results. not tested in production. table 44. oscillator current consumption symbol parameter conditions typ max (1) unit i dd(osc) hse oscillator current consumption (2) quartz or ceramic resonator, cl = 33 pf v dd = 5 v f osc = 24 mhz 1 2.0 (3) ma f osc = 16 mhz 0.6 ? f osc = 8 mhz 0.57 ? i dd(osc) hse oscillator current consumption (2) quartz or ceramic resonator, cl = 33 pf v dd = 3.3 v f osc = 24 mhz 0.5 1.0 (3) f osc = 16 mhz 0.25 ? f osc = 8 mhz 0.18 ? 1. during startup, the oscillator current consumption may reach 6 ma. 2. the supply current of the os cillator can be further optimi zed by selecting a high qua lity resonator with small r m value. refer to crystal manufacturer for more details 3. informative data. table 45. programming current consumption symbol parameter conditions typ max unit i dd(prog) programming current v dd = 5 v, -40 c to 150 c, erasing and programming data or program memory 1.0 1.7 ma
electrical characteristics stm8af52/62xx, stm8af51/61xx 72/120 doc id 14395 rev 7 current consumption curves figure 14 to figure 19 show typical current consumption measured with code executing in ram. table 46. typical peripheral current consumption v dd = 5.0 v (1) symbol parameter typ. f master = 2 mhz typ. f master = 16 mhz typ. f master =24 mhz unit i dd(tim1) tim1 supply current (2) 0.03 0.23 0.34 ma i dd(tim2) tim2 supply current (2) 0.02 0.12 0.19 i dd(tim3) tim3 supply current (2) 0.01 0.1 0.16 i dd(tim4) tim4 supply current (2) 0.004 0.03 0.05 i dd(usart) usart supply current (2) 0.03 0.09 0.15 i dd(linuart) linuart supply current (2) 0.03 0.11 0.18 i dd(spi) spi supply current (2) 0.01 0.04 0.07 i dd(i 2 c) i 2 c supply current (2) 0.02 0.06 0.91 i dd(can) can supply current (3) 0.06 0.30 0.40 i dd(awu) awu supply current (2) 0.003 0.02 0.05 i dd(tot_dig) all digital peripherals on 0.22 1 2.4 i dd(adc) adc supply current when converting (4) 0.93 0.95 0.96 1. typical values not tested in producti on. since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are simi lar in the full supply voltage range. 2. data based on a differential i dd measurement between no peripheral clock ed and a single active peripheral. this measurement does not include t he pad toggling consumption. 3. data based on a differential idd measurement between rese t configuration (can disabl ed) and a permanent can data transmit sequence in loopback mode at 1 mhz. this me asurement does not include the pad toggling consumption. 4. data based on a differential i dd measurement between reset configurat ion and continuous a/d conversions. figure 14. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripherals = on figure 15. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, peripherals = on 0 1 2 3 4 5 6 7 8 9 10 2.533.544.555.56 v dd [v] i dd(run)hse [ma] 25c 85c 12 5 c 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 fcpu [mhz] i dd(run)hse [ma] 25c 85c 12 5 c
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 73/120 figure 16. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, peripherals = off figure 17. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, peripherals = on 0 1 2 3 4 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(run)hsi [ma] 25c 85c 125c 0 1 2 3 4 5 6 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(wfi)hse [ma] 25c 85c 125c figure 18. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, peripherals = on figure 19. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, peripherals = off 0 1 2 3 4 5 6 0 5 10 15 20 25 30 fcpu [mhz] i dd(wfi)hse [ma] 25c 85c 12 5 c 0 0. 5 1 1. 5 2 2. 5 2.533.544.555.56 v dd [v] i dd(wfi)hsi [ma] 25c 85c 12 5 c
electrical characteristics stm8af52/62xx, stm8af51/61xx 74/120 doc id 14395 rev 7 10.3.3 external clock sources and timing characteristics hse external clock an hse clock can be generated by feeding an external clock signal of up to 24 mhz to the oscin pin. clock characteristics are subject to general operating conditions for v dd and t a . figure 20. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied using a crystal/ce ramic resonator oscillator of up to 24 mhz. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). table 47. hse external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency t a = -40 c to 150 c 0 (1) ?24 (2) mhz v hsedhl comparator hysteresis ? 0.1 x v dd ?? v v hseh oscin high-level input pin voltage ? 0.7 x v dd ?v dd v hsel oscin low-level input pin voltage ?v ss ? 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 ? +1 a 1. if css is used, the external clock must have a frequency above 500 khz. 2. for devices with less than 96 kbyte of program memory, the 24 mhz are only achievable using the super set silicon (salestype contains sss) oscin f hse external clock stm8a source v hsel v hseh
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 75/120 figure 21. hse oscillator circuit diagram hse oscillator critical g m formula the crystal characteristics have to be checked with the following formula: equation 1 where g mcrit can be calculated with the crystal parameters as follows: equation 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co : shunt capacitance (see crystal specification) c l1 = c l2 = c : grounded external capacitance table 48. hse oscillator characteristics symbol parameter conditions min typ max unit r f feedback resistor ? ? 220 ? k c l1 /c l2 (1) recommended load capacitance ? ? ? 20 pf g m oscillator trans conductance ? 5 ? ? ma/v t su(hse) (2) startup time v dd is stabilized ?2.8 ?ms 1. the oscillator needs two load capacitors, c l1 and c l2 , to act as load for the crystal. the total load capacitance (cload) is (c l1 * c l2 )/(c l1 + c l2 ). if c l1 = c l2 , cload = c l1/2 . some oscillators have bu ilt-in load capacitors, c l1 and c l2 . 2. this value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 mhz oscillation is reached. it can vary with the crystal type that is used. oscout oscin f hse to core c l1 c l2 r f stm8a resonator current control g m r m c m l m c o resonator g m g mcrit ? g mcrit 2 hse f () 2 r m 2co c + () 2 =
electrical characteristics stm8af52/62xx, stm8af51/61xx 76/120 doc id 14395 rev 7 10.3.4 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high-speed internal rc oscillator (hsi) figure 22. typical hsi frequency vs v dd table 49. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency ? ? 16 ? mhz acc hs hsi oscillator user trimming accuracy trimmed by the application for any v dd and t a conditions -1 ? 1 % hsi oscillator accuracy (factory calibrated) v dd = 3.0 v v dd 5.5 v, -40 c t a 150 c -5 ? 5 t su(hsi) hsi oscillator wakeup time ? ? ? 2 (1) 1. guaranteed by characterizati on, not tested in production s -3% -2% -1% 0% 1% 2% 3% 2.533.544.555.56 v dd [v] hsi frequency variation [%] -40c 25c 85c 125c
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 77/120 low-speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 23. typical lsi frequency vs v dd table 50. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency ? 112 128 144 khz t su(lsi) lsi oscillator wakeup time ? ? ? 7 (1) 1. data based on characterization results, not tested in production. s -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] lsi frequency variation [%] 25c
electrical characteristics stm8af52/62xx, stm8af51/61xx 78/120 doc id 14395 rev 7 10.3.5 memory characteristics flash program memory/data eeprom memory general conditions: t a = -40 c to 150 c. table 51. flash program memory/data eeprom memory symbol parameter conditions min (1) 1. guaranteed by characterizati on, not tested in production. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu is 16 to 24 mhz with 1 ws (2) f cpu is 0 to 16 mhz with 0 ws 2. for devices with less than 96 kbyte of program me mory, the 24 mhz are only ac hievable using the super set silicon (salestype contains sss) 3.0 ? 5.5 v v dd operating voltage (code execution) f cpu is 16 to 24 mhz with 1 ws (2) f cpu is 0 to 16 mhz with 0 ws 2.6 ? 5.5 t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) ??66.6 ms fast programming time for 1 block (128 bytes) ??33.3 t erase erase time for 1 block (128 bytes) ? ? 3 3.3 ms table 52. program memory symbol parameter condition min max unit t we temperature for writing and erasing ? -40 125 c n we program memory endurance (erase/write cycles) (1) 1. the physical granularity of the memo ry is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 1000 ? cycles t ret data retention time t a = 25 c 40 ? years t a = 55 c 20 ?
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 79/120 table 53. data memory symbol parameter condition min max unit t we temperature for writing and erasing ? -40 125 c 150 (1) 1. target value, to be confirmed. n we data memory endurance (2) (erase/write cycles) 2. the physical granularity of the memo ry is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 300 k ? cycles t a = -40c to 125 c 100 k (3) 3. more information on the relationship between data re tention time and number of write/erase cycles is available in a separat e technical document. ? t ret data retention time t a = 25 c 40 (3)(4) 4. retention time for 256b of data memory after up to 1000 cycles at 125 c. ? years t a = 55 c 20 (3)(4) ?
electrical characteristics stm8af52/62xx, stm8af51/61xx 80/120 doc id 14395 rev 7 10.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage, using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 54. i/o static characteristics symbol parameter conditions min typ max unit v il low-level input voltage ? -0.3 v 0.3 x v dd ? v ih high-level input voltage 0.7 x v dd v dd + 0.3 v v hys hysteresis (1) ? 0.1 x v dd ? v oh high-level output voltage standard i/0, v dd = 5 v, i = 3 ma v dd - 0.5 v ? ? standard i/0, v dd = 3 v, i = 1.5 ma v dd - 0.4 v ? ? v ol low-level output voltage high sink and true open drain i/0, v dd = 5 v i = 8 ma ??0.5 v standard i/0, v dd = 5 v i = 3 ma ??0.6 standard i/0, v dd = 3 v i = 1.5 ma ??0.4 r pu pull-up resistor v dd = 5 v, v in = v ss 35 50 65 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf ??20 (2) ns standard and high sink i/os load = 50 pf ? ? 125 (2) i lkg digital input pad leakage current v ss v in v dd ??1a i lkg ana analog input pad leakage current v ss v in v dd -40 c < t a < 125 c ? ? 250 na v ss v in v dd -40 c < t a < 150 c ? ? 500 i lkg(inj) leakage current in adjacent i/o (2) injection current 4 ma ? ? 1 (2) a i ddio total current on either v ddio or v ssio including injection currents ? ? 60 ma 1. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production. 2. data based on characterization results, not tested in production.
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 81/120 figure 24. typical v il and v ih vs v dd @ four temperatures figure 25. typical pull-up resistance r pu vs v dd @ four temperatures 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c 30 35 40 45 50 55 60 2.53 3.544.55 5.56 v dd [v] pull-up resistance [k ohm ] -40c 25c 85c 125c
electrical characteristics stm8af52/62xx, stm8af51/61xx 82/120 doc id 14395 rev 7 figure 26. typical pull-up current i pu vs v dd @ four temperatures (1) 1. the pull-up is a pure resi stor (slope goes through 0). typical output level curves figure 27 to figure 36 show typical output level curves measured with output on a single pin. 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40c 25c 85c 125c figure 27. typ. v ol @ v dd = 3.3 v (standard ports) figure 28. typ. v ol @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 024681012 i ol [ma] v ol [v] -40c 25c 85c 125c figure 29. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 30. typ. v ol @ v dd = 5.0 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 83/120 figure 31. typ. v ol @ v dd = 3.3 v (high sink ports) figure 32. typ. v ol @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c figure 33. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 34. typ. v dd - v oh @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c figure 35. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) figure 36. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c
electrical characteristics stm8af52/62xx, stm8af51/61xx 84/120 doc id 14395 rev 7 10.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 37. typical nrst v il and v ih vs v dd @ four temperatures table 55. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst low-level input voltage (1) 1. data based on characterization results, not tested in production. ?v ss ? 0.3 x v dd ? v ih(nrst) nrst high-level input voltage (1) ? 0.7 x v dd ?v dd v ol(nrst) nrst low-level output voltage (1) i ol = 3 ma ? 0.6 v r pu(nrst) nrst pull-up resistor ? 30 40 60 k v f(nrst) nrst input filtered pulse (1) ?85?315ns 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 85/120 figure 38. typical nrst pull-up resistance r pu vs v dd figure 39. typical nrst pull-up current i pu vs v dd the reset network shown in figure 40 protects the device against parasitic resets. figure 40. recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] nrst pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] nrst pull-up current [a] -40c 25c 85c 125c external reset circuit stm8a filter r pu v dd internal reset nrst 0.01
electrical characteristics stm8af52/62xx, stm8af51/61xx 86/120 doc id 14395 rev 7 10.3.8 tim 1, 2, 3, and 4 electrical specifications subject to general operating conditions for v dd , f master and t a . table 56. tim 1, 2, 3, and 4 electrical specifications symbol parameter conditions min typ max unit f ext timer external clock frequency (1) 1. not tested in production. for devices with less t han 96 kbyte of program memory, the 24 mhz are only achievable using the super set si licon (salestype contains sss). ???24mhz
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 87/120 10.3.9 spi interface unless otherwise specified, the parameters given in ta bl e 5 7 are derived from tests performed under ambient temperature, f master frequency, and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss , sck, mosi, miso). table 57. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode v dd < 4.5 v 0 6 (1) v dd = 4.5 v to 5.5 v 0 8 (1) t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf ? 25 (2) ns t su(nss) (3) nss setup time slave mode 4 * t master ? t h(nss) (3) nss hold time slave mode 70 ? t w(sckh) (3) t w(sckl) (3) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 110 140 t su(mi) (3) t su(si) (3) data input setup time master mode 5 ? slave mode 5 ? t h(mi) (3) t h(si) (3) data input hold time master mode 7 ? slave mode 10 ? t a(so) (3)(4) data output access time slave mode ? 3* t master t dis(so) (3)(5) data output disable time slave mode 25 t v(so) (3) data output valid time slave mode (after enable edge) v dd < 4.5 v ? 75 v dd = 4.5 v to 5.5 v ? 53 t v(mo) (3) data output valid time master mode (after enable edge) ? 30 t h(so) (3) data output hold time slave mode (after enable edge) 31 ? t h(mo) (3) master mode (after enable edge) 12 ? 1. f max is f master /2. 2. the pad has to be configured accordingly (fast mode). 3. values based on design simulation and/or charac terization results, and not tested in production. 4. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z.
electrical characteristics stm8af52/62xx, stm8af51/61xx 88/120 doc id 14395 rev 7 figure 41. spi timing diagram in slave mode and with cpha = 0 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . figure 42. spi timing diagram in slave mode and with cpha = 1 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 89/120 figure 43. spi timing diagram - master mode 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm8af52/62xx, stm8af51/61xx 90/120 doc id 14395 rev 7 10.3.10 i 2 c interface characteristics table 58. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 ? 1.3 ? s t w(sclh) scl clock high time 4.0 ? 0.6 ? t su(sda) sda setup time 250 ? 100 ? ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time ?0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time (v dd 3 v to 5.5 v) ? 1000 ? 300 t f(sda) t f(scl) sda and scl fall time (v dd 3 v to 5.5 v) ? 300 ? 300 t h(sta) start condition hold time 4.0 ? 0.6 ? s t su(sta) repeated start condition setup time 4.7 ? 0.6 ? t su(sto) stop condition setup time 4.0 ? 0.6 ? s t w(sto:sta) stop to start condition time (bus free) 4.7 ? 1.3 ? s c b capacitive load for each bus line ? 400 ? 400 pf
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 91/120 10.3.11 10-bit adc characteristics subject to general operating conditions for v dda , f master and t a unless otherwise specified. figure 44. typical application with adc 1. legend: r ain = external resistance, c ain = capacitors, c samp = internal sample and hold capacitor. table 59. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency ? 111 khz ? 4 mhz khz/mhz v dda analog supply ? 3 ? 5.5 v v ref+ positive reference voltage ? 2.75 ? v dda v ref- negative reference voltage ? v ssa ? 0.5 v ain conversion voltage range (1) 1. during the sample time, the sampling capacitance, c samp (3 pf typ), can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. ?v ssa ?v dda devices with external v ref+ / v ref- pins v ref- ?v ref+ c samp internal sample and hold capacitor ? ? ? 3 pf t s (1) sampling time (3 x 1/f adc ) f adc = 2 mhz ? 1.5 ? s f adc = 4 mhz ? 0.75 ? t stab wakeup time from standby f adc = 2 mhz ? 7 ? f adc = 4 mhz 3.5 t conv total conversion time including sampling time (14 x 1/f adc ) f adc = 2 mhz ? 7 ? f adc = 4 mhz ? 3.5 ? r switch equivalent switch resistance ? ? ? 30 k ainx stm8a v dd i l v t 0.6v v t 0.6v v ain r ain 10-bit a/d conversion c ain t s c samp rswitch
electrical characteristics stm8af52/62xx, stm8af51/61xx 92/120 doc id 14395 rev 7 figure 45. adc accura cy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the fi rst actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum dev iation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. table 60. adc accuracy for v dda = 5 v symbol parameter conditions typ max (1) 1. max value is based on characte rization, not tested in production. unit |e t | total unadjusted error (2) 2. adc accuracy vs. injection current: any positive or negat ive injection current within the limits specified for i inj(pin) and i inj(pin) in section 10.3.6 does not affect the adc accuracy. f adc = 2 mhz 1.4 3 (3) 3. tue 2lsb can be reached on specific salestypes in the whole temperature range. lsb |e o | offset error (2) 0.8 3 |e g | gain error (2) 0.1 2 |e d | differential linearity error (2) 0.9 1 |e l | integral linearity error (2) 0.7 1.5 |e t | total unadjusted error (2) f adc = 4 mhz 1.9 (4) 4. target values. 4 (4) |e o | offset error (2) 1.3 (4) 4 (4) |e g | gain error (2) 0.6 (4) 3 (4) |e d | differential linearity error (2) 1.5 (4) 2 (4) |e l | integral linearity error (2) 1.2 (4) 1.5 (4) e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 93/120 10.3.12 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 61. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-4 4a
electrical characteristics stm8af52/62xx, stm8af51/61xx 94/120 doc id 14395 rev 7 electromagnetic interference (emi) emission tests conform to the sae j 1752/3 standard for test software, board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (3 positive then 3 n egative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 62. emi data symbol parameter conditions unit general conditions monitored frequency band max f cpu (1) 1. data based on characterization results, not tested in production. 8 mhz 16 mhz 24 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp80 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 15 17 22 dbv 30 mhz to 130 mhz 18 22 16 130 mhz to 1 ghz -1 3 5 sae emi level ? 2 2.5 2.5 table 63. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production uni t v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c, conforming to jesd22-a114 3a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25 c, conforming to jesd22-c101 3 500 v esd(mm) electrostatic discharge voltage (charge device model) t a = 25 c, conforming to jesd22-a115 b200
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 95/120 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 64. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu static latch-up class t a = 25 c a t a = 85 c t a = 125 c t a = 150 c
electrical characteristics stm8af52/62xx, stm8af51/61xx 96/120 doc id 14395 rev 7 10.4 thermal characteristics in case the maximum chip junction temperature (t jmax ) specified in table 40: general operating conditions is exceeded, the functionality of the device cannot be guaranteed. t jmax , in degrees celsius, may be calculated using the following equation: equation 3 t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: equation 4 p i/omax = (v ol * i ol ) + ((v dd - v oh ) * i oh ) taking into account the actual v ol / i ol and v oh / i oh of the i/os at low- and high-level in the application. 10.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 65. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 80 - 14 x 14 mm 38 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm 46 c/w ja thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 59 c/w
stm8af52/62xx, stm8af51/61xx electrical characteristics doc id 14395 rev 7 97/120 10.4.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the order code (see figure 50: ordering information scheme(1) on page 103 ). the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: ? maximum ambient temperature t amax = 82 c (measured according to jesd51-2) ?i ddmax = 8 ma ?v dd = 5 v ? maximum 20 i/os used at the same time in output at low-level with i ol = 8 ma ?v ol = 0.4 v equation 5 p intmax = 8 ma x 5 v = 400 mw equation 6 p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw: equation 7 p dmax = 400 mw + 64 mw thus: p dmax = 464 mw. using the values obtained in table 65: thermal characteristics on page 96 t jmax is calculated as follows: for lqfp64 46 c/w equation 8 t jmax = 82 c + (46 c/w x 464 mw) = 82 c + 21 c = 103 c this is within the range of the suffix b version parts (-40 c < t j < 105 c). parts must be ordered at least with the temperature range suffix b.
package characteristics stm8af52/62xx, stm8af51/61xx 98/120 doc id 14395 rev 7 11 package characteristics 11.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm8af52/62xx, stm8af51/61xx package characteristics doc id 14395 rev 7 99/120 11.2 package mechanical data figure 46. 80-pin low profile quad flat package (14 x 14) table 66. 80-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.60 ? ? 0.0630 a1 0.05 ? 0.15 0.0020 ? 0.0060 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.22 0.32 0.38 0.0087 0.0126 0.0150 c 0.09 ? 0.20 0.0035 ? 0.0079 d 15.80 16.00 16.20 0.6220 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 ? 12.35 ? ? 0.4862 ? e 15.80 16.00 16.20 0.6220 0.6299 0.6378 e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 ? 12.35 ? ? 0.4862 ? e ? 0.65 ? ? 0.0256 ? l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 ? 1.00 ? ? 0.0394 ? ccc ? ? 0.10 ? ? 0.0039 k 03.57 03.57 1s_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 40 41 60 61 b 80 1 pin 1 identification
package characteristics stm8af52/62xx, stm8af51/61xx 100/120 doc id 14395 rev 7 figure 47. 64-pin low profile quad flat package (10 x 10) table 67. 64-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.60 ? ? 0.0630 a1 0.05 ? 0.15 0.0020 ? 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 ? 0.20 0.0035 ? 0.0079 d ? 12.00 ? ? 0.4724 ? d1 ? 10.00 ? ? 0.3937 ? e ? 12.00 ? ? 0.4724 ? e1 ? 10.00 ? ? 0.3937 ? e ? 0.50 ? ? 0.0197 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 ? 1.00 ? ? 0.0394 ? l1 l a a2 a1 b e c d d1 e e1 pin 1 identification m x 45? seating plane (0.1 x 0.004 mm)
stm8af52/62xx, stm8af51/61xx package characteristics doc id 14395 rev 7 101/120 figure 48. 48-pin low profile quad flat package (7 x 7) table 68. 48-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.60 ? ? 0.0630 a1 0.05 ? 0.15 0.0020 ? 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 ? 0.20 0.0035 ? 0.0079 d ? 9.00 ? ? 0.3543 ? d1 ? 7.00 ? ? 0.2756 ? e ? 9.00 ? ? 0.3543 ? e1 ? 7.00 ? ? 0.2756 ? e ? 0.50 ? ? 0.0197 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 ? 1.00 ? ? 0.0394 ? e e1 d d1 l1 l c e b a1 a2 a
package characteristics stm8af52/62xx, stm8af51/61xx 102/120 doc id 14395 rev 7 figure 49. 32-pin low profile quad flat package (7 x 7) table 69. 32-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.60 ? ? 0.0630 a1 0.05 ? 0.15 0.0020 ? 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 ? 0.20 0.0035 ? 0.0079 d ? 9.00 ? ? 0.3543 ? d1 ? 7.00 ? ? 0.2756 ? e ? 9.00 ? ? 0.3543 ? e1 ? 7.00 ? ? 0.2756 ? e ? 0.80 ? ? 0.0315 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 ? 1.00 ? ? 0.0394 ? c l l1 b e a1 a2 a e e1 d d1
stm8af52/62xx, stm8af51/61xx ordering information doc id 14395 rev 7 103/120 12 ordering information figure 50. ordering information scheme (1) 1. customer specific fastrom code or custom device co nfiguration. this field shows ?sss? if the device contains a super set sili con, usually equipped with bigger memory and more i/os. this silicon is supposed to be replaced later by the target silicon. 2. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. 3. not recommended for new design. stm8a f 61 a a t d xxx (1) y product class 8-bit automotive microcontroller program memory size 6 = 32 kbytes 7 = 48 kbytes 8 = 64 kbytes 9 = 96 kbytes a= 128 kbytes package type t = lqfp example: device family 52 = silicon rev w, can/lin 62 = silicon rev w, lin only 51 = silicon rev x, can/lin 61 = silicon rev x, lin only (3) program memory type f = flash + eeprom p = fastrom h = flash no eeprom (3) temperature range a = -40 to 85 c b = -40 to 105 c c = -40 to 125 c d= -40 to 150 c pin count 6 = 32 pins 8 = 48 pins 9= 64 pins a = 80 pins packing y = tray u = tube x = tape and reel compliant with eia 481-c
known limitations stm8af52/62xx, stm8af51/61xx 104/120 doc id 14395 rev 7 13 known limitations ta bl e 7 0 gives a summary of the fix status. table 70. product evolution summary section limitation rev x rev w stm8a core section 13.1.1 wait for event instruction (wfe) not available not fixed not fixed section 13.1.2 jril and jrih instructions not available section 13.1.3 cpu not returning to halt mode when the al bit is set section 13.1.4 main program not resuming after isr has reset the al bit i 2 c interface section 13.2.1 misplaced nack bit when receiving 2 bytes in master mode not fixed not fixed section 13.2.2 data register corrupted section 13.2.3 delay in stop bit programming leading to reception of supplementary byte section 13.2.4 start condition badly generated after misplaced stop usart interface section 13.3.1 parity error flag (pe) not correctly set when overrun condition occurs not fixed not fixed linuart interface section 13.4.1 framing error with data byte 0x00 not fixed not fixed section 13.4.2 framing error when receiving an identifier (id) section 13.4.3 parity error when receiving an identifier (id) section 13.4.4 or flag not correctly set in lin master mode section 13.4.5 lin header error when automatic resynchronization is enabled fixed clock controller section 13.5.1 hsi rc oscillator ca nnot be switched off in run mode not fixed not fixed spi interface section 13.6.1 last bit too short if spi is disabled during communication not fixed not fixed
stm8af52/62xx, stm8af51/61xx known limitations doc id 14395 rev 7 105/120 13.1 stm8a core 13.1.1 wait for event instru ction (wfe) not available description the wfe instruction is not implemented in the devices covered by this datasheet. this instruction is used to synchronize the device with external computing resources. for further details on this instruction, refer to the stm8 cpu programming manual (pm0044) on www.st.com . workaround none. 13.1.2 jril and jrih inst ructions not available description jril (jump if port int pin = 0) and jrih (jump if port int pin = 1) are not supported by the devices covered by this datasheet. these instructions perform conditional jumps: jril and jrih jump if one of the external interrupt lines is low and high, respectively. in the devices covered by this datasheet, jril is equivalent to an unconditional jump and jrih is equivalent to nop. for further details on these instructions, refer to the stm8 cpu programming manual (pm0044) on www.st.com . workaround none. becan interface section 13.7.1 becan transmission error when sleep mode is entered during transmission not fixed not fixed section 13.7.2 becan woken up from sleep mode with automatic wakeup interrupt section 13.7.3 becan time triggered communication mode not supported section 13.7.4 becan transmitted data corruption fixed section 13.7.5 be can read error in slow mode not fixed table 70. product evolution summary section limitation rev x rev w
known limitations stm8af52/62xx, stm8af51/61xx 106/120 doc id 14395 rev 7 13.1.3 cpu not return ing to halt mode when the al bit is set description when the al bit of the cfg_gcr register is set, the cpu does not return to halt mode after exiting an interrupt service routine (isr). it returns to the main program and executes the next instruction after the halt instruction. workaround none. 13.1.4 main program not resuming after isr has r eset the al bit description if the cpu is in wait for interrupt state and the al bit is set, the cpu returns to wait for interrupt state after executing an isr. to continue executing the main program, the al bit must be reset by the isr. when al is reset just before exiting the isr, the cpu may remain stalled. workaround reset the al bit at least two instructions before the iret instruction. 13.2 i 2 c interface 13.2.1 misplaced nack bit when r eceiving 2 bytes in master mode description when receiving two bytes in master mode, the usual sequence is the following: 1. set pos and ack bits of the i2c_cr2 register to 1. 2. wait for addr event (address sent bit in i2c_sr1 register). when addr is set to 1, program ack to 0 and clear addr. 3. wait for btf event (byte transfer finished bit in i2c_sr1 register). when btf is set to 1, program the stop bit to 1 in the i2c_cr2 register, and read the 2 received bytes. the nack bit may be sent erroneously after the first byte. workaround use a different software sequence to clear addr and ack bits: 1. wait till addr flag is set. 2. mask interrupts. 3. clear addr bit. 4. clear ack bit. 5. re-enable interrupts. as the tli interrupt is not maskable, this software workaround can not be implemented in applications using the tli interrupt.
stm8af52/62xx, stm8af51/61xx known limitations doc id 14395 rev 7 107/120 13.2.2 data register corrupted description the content of the shift register may be shifted to the left by 1 bit and the second read operation will return an in correct value when the following conditions are met: btf bit (last data received) set to 1 software sequence (set stop, read n-1, read n) delayed (for instance by an interrupt) n-1 byte not read before the next scl rising edge. workaround mask all active interrupts between the set stop and the read n-1 instructions. as tli is not maskable, this software workaround can not be implemented in applications using the tli interrupt. 13.2.3 delay in stop bit programming leading to recepti on of supplementary byte description when receiving one byte in master mode, the stop bit in the i2c_cr2 register is programmed just after addr bit is cleared in order to generate a stop condition after the reception of the byte. if the programming of the stop bit is delayed after the end of the first byte reception, the master may receive another byte before the stop condition is generated and a wrong data will be received. workaround mask interrupts while clearing the addr bit and programming the stop bit. as tli is not maskable, this software workaround can not be implemented in applications using the tli interrupt. 13.2.4 start condition badly gener ated after misplaced stop description when the start bit is set in the i2c_cr2 register and a misplaced stop occurs on the bus thus leading to a bus error, the start condition on the bus may be badly generated by the i 2 c peripheral (glitch on sda resulting in sda and scl tied low simultaneously). workaround when a bus error is detected (through a flag and/or interrupt), check if a start condition was requested through the i2c_cr2 register. if so, a stop condition should be generated followed by a new start condition. this does not avoid the badly generated start condition, but allows to resynchronize the network on the new start condition.
known limitations stm8af52/62xx, stm8af51/61xx 108/120 doc id 14395 rev 7 13.3 usart interface 13.3.1 parity error flag (pe) not co rrectly set when o verrun condition occurs description if an overrun condition occurs, the parity error flag (pe) of the uart_sr register is not set for the frame which caused the overrun condition. the pe flag represents the status of the last correctly received frame. workaround none. 13.4 linuart interface 13.4.1 framing error with data byte 0x00 description if the linuart interface is configured in lin slave mode, and the active mode with break detection length is set to 11 (lbdl bit of uart_cr4 register set to 1), fe and rxne flags are not set when receiving a 0x00 data byte with a framing error, followed by a recessive state. this occurs only if the dominant state length is between 9.56 and 10.56 times the baud rate. workaround the lin software driver can handle this exceptional case by implementing frame timeouts to comply with the lin standard. this method has been implemented in st lin 2.1 driver package which passed the lin compliance tests. 13.4.2 framing error when re ceiving an identifier (id) description if an id framing error occurs when the linuart is in active mode, both lhe and lhdf flags are set at the end of the lin header with id framing error. workaround the lin software driver can handle this case by checking both lhe and lhdf flags upon header reception. 13.4.3 parity error when re ceiving an identifier (id) description if an id parity error occurs, the linuart wakes up from mute mode and both lhe and lhdf are set at the end of the lin header with parity error. the pe flag is also set.
stm8af52/62xx, stm8af51/61xx known limitations doc id 14395 rev 7 109/120 workaround the lin software driver can handle this case by checking all the flags upon header reception. 13.4.4 or flag not correctly set in lin master mode description when the linuart operates in master mode, the or flag is not set if an overrun condition occurs. workaround the lin software driver can detect this case through a lin protocol error. 13.4.5 lin header error when automat ic resynchronization is enabled description if the linuart is configured in lin slave mode (lslv bit set in linuart_cr6 register) and the automatic resynchr onization is enabled (lase bit set in linuart_cr6), the lhe flag may be set instead of lhdf flag when receiving a valid header. this limitation is fixed in silicon revision w. workaround none. 13.5 clock controller 13.5.1 hsi rc oscillator cannot be switched off in run mode description the internal 16 mhz rc oscillator cannot be s witched off in run mode, even if the hsien bit is programmed to 0. workaround none. 13.6 spi interface 13.6.1 last bit too short if spi is disabled during communication description when the spi interface operates in master mode and the baud rate generator prescaler is equal to 2, the spi is disabled during ongoing communications, and the data and clock output signals are switched off at the last strobing edge of the spi clock.
known limitations stm8af52/62xx, stm8af51/61xx 110/120 doc id 14395 rev 7 as a consequence the length of the last bit is out of range and its reception on the bus is not ensured. workaround check if a communication is ongoing before disabling the spi interface. this can be done by monitoring the bsy bit in the spi_sr register. 13.7 becan interface 13.7.1 becan transmission error when sleep mode is entered during transmission description if sleep mode entry is requested while a transm ission is ongoing or a transmission request is pending, the becan t x pin will have a spurious behavior incompliant with the can protocol. no error frame will be sent and the device will enter sleep mode. workaround ensure that no transmission is ongoing and th at no transmission request is pending before putting the becan in sleep mode. this can be done by checking the becan control and status registers before entering sleep mode. refer to section 24.4.3 sleep mode (low power) of the rm0009 reference manual. 13.7.2 becan woken up from sleep mode with automatic wakeup interrupt description waking up the becan from sleep mode using the automatic wakeup interrupt triggers an interrupt on each can rx falli ng edge until the bus is idle. workaround to have a wakeup interrupt triggered only on the first falling edge of the can rx pin, perform the following actions: 1. disable the automatic wakeup interrupt. 2. clear the wkui flag. 3. disable the sleep mode in the isr. 13.7.3 becan time triggered communication mode not supported description the time triggered communication mode described in section 24.4.4 of the stm8a reference manual (rm0009) is not supported.
stm8af52/62xx, stm8af51/61xx known limitations doc id 14395 rev 7 111/120 ttcm bit must be kept at 0 in the can_mcr register (time triggered communication mode disabled). workaround none. 13.7.4 becan transmitted data corruption description the tgt bit can be set to 1 (can_mtsrh and can_mtsrl registers sent) even if the device is not in time triggered communication mode (ttcm set to 1). this is due to the fact that the can_mdlcr register reset value is undefined, causing the tgt bit to be set to 1 whatever the value of ttcm. this leads to the corruption of last two data bytes sent. workaround tgt bit in can_mdlcr must be initialized to 0 (can_mtsrh and can_mtsrl registers not sent). 13.7.5 be can read er ror in slow mode description the read byte may be corrupted when the cpu is in slow mode and a fifo read operation is performed while a message transmission is ongoing. this happens because the transmission mailboxes and the receive fifos share the same address/data lines for read and write operations. workaround to prevent this problem from occurring, the cpu clock must be the master clock (clk_ckdivr[2:0] = 000b) when the user application starts reading the fifo (cpu clock divider changed to /1). after the fifo read operation is complete, the cpu clock divider (slow mode) could be applied again.
stm8 development tools stm8af52/62xx, stm8af51/61xx 112/120 doc id 14395 rev 7 14 stm8 development tools development tools for the stm8a microcontrollers include the stice emulation system offeri ng tracing and code profiling stvd high-level language debugger including assembler and visual development environment - seamless integration of third party c compilers stvp flash programming software in addition, the stm8a comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 14.1 emulation and in-circuit debugging tools the stm8 tool line includes the stice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition, stm8a application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full-featured emulators from stmicroelectronics. it offers new advanced debugging capabilities incl uding tracing, profilin g and code coverage analysis to help detect execution bottlenecks and dead code. in addition, stice offers in-circuit debugging and programming of stm8a microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. 14.1.1 stice key features program and data trace recording up to 128 k records advanced breakpoints with up to 4 levels of conditions data breakpoints real-time read/write of all device resources during emulation occurrence and time profiling and code coverage analysis (new features) in-circuit debugging/programming via swim protocol 8-bit probe analyzer 1 input and 2 output triggers usb 2.0 high-speed interface to host pc power supply follower managing application voltages between 1.62 to 5.5 v modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8.
stm8af52/62xx, stm8af51/61xx stm8 development tools doc id 14395 rev 7 113/120 14.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st visual develop (stvd) ide and the st visual program- mer (stvp) software interface. stvd provides seamless integration of the cosmic c com- piler for stm8, which is available in a free version that outputs up to 16 kbytes of code. 14.2.1 stm8 toolset the stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: st visual develop full-featured integrated development environment from stmicroelectronics, featuring: seamless integration of c and asm toolsets full-featured debugger project management syntax highlighting editor integrated programming interface support of advanced emulation features fo r stice such as code profiling and coverage st visual programmer (stvp) easy-to-use, unlimited graphical interface allowing read, write and verification of the stm8a microcontroller?s flash memory. stvp also of fers project mode for saving programming configurations and automating programming sequences. 14.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: c compiler for stm8 available in a free version that outputs up to 16 kbytes of code. for more information, see www.cosmic-software.com, www.raisonance.com stm8 assembler linker free assembly toolchain included in the stm8 toolset, which allows you to assemble and link your application source code.
stm8 development tools stm8af52/62xx, stm8af51/61xx 114/120 doc id 14395 rev 7 14.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8a flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8a. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family.
stm8af52/62xx, stm8af51/61xx revision history doc id 14395 rev 7 115/120 15 revision history table 71. document revision history date revision changes 31-jan-2008 rev 1 initial release 22-aug-2008 rev 2 added ?h? products to the datasheet (flash no eeprom). features on page 1 : updated memories , reset and supply management , communication interfaces and ; reduced wakeup pins by 1. ta bl e 1 : removed stm8af6168, stm8af6148, stm8af6166, stm8af6146, stm8af5168, st m8af5186, stm8af5176, and stm8af5166. section 1 , section 5 , section 6.2 , ta b l e 3 5 , and section 9 : updated reference documentation: rm0009, pm0047, and um0470. section 2 : added information about peak performance. section 3 : removed stm8a common features table. ta bl e 4 : removed stm8af5186t, stm8af5176t, stm8af5168t, and stm8af5166t. ta bl e 5 : removed stm8af6168t, stm8af6166t, stm8af6148t, and stm8af6146t. section 5 : made minor content changes and improved readability and layout. section 5.5.3 : major modification, tmu included. section 5.5.2 : user trimming updated. section 5.5.3 : lsi as cpu clock added. section 5.5.4 , section 5.5.5 : maximum frequency conditional 32 kbyte/128 kbyte. section 5.8 : scan for 128 kbyte removed. section 5.9 , section 5.9.3 : spi 10 mb/s. figure 3 , figure 4 , and figure 5 : amended footnote 1. ta bl e 8 : hs output changed from 20 ma to 8 ma. section 7 : corrected figure 7: register and memory map ; removed address list; added ta bl e 1 0 . section 10.3.2 note on typical/wc values added. ta bl e 1 6 : replaced the source blocks ?simple usart?, ?very low-end timer (timer 4)?, and ?eeprom? with ?linuart?, ?timer4? and ?reserved? respectively, added tmu registers. ta bl e 3 4 : updated opt6 and nopt6, added opt7 to 17 (tmu, bl) ta bl e 3 5 : updated opt1 ubc[7:0], opt4 ckawusel, opt4 prsc [1:0], and opt6, added opt7 to 16 (tmu). ta bl e 3 7 : amended footnotes. ta bl e 4 0 : added parameter ?voltage and current operating conditions?. ta bl e 4 1 : amended footnotes. ta bl e 4 2 : replaced. ta bl e 4 3 : amended maximum data and footnotes. table 21 : replaced. ta bl e 2 2 : added and amended i dd(run) data; amended i dd(wfi) data; amended footnotes. ta bl e 4 6 : filled in, amended maximum data and footnotes. figure 14 to figure 19 : info on peripheral activity added. ta bl e 4 7 : modified f hse_ext data and added v hsedhl data.
revision history stm8af52/62xx, stm8af51/61xx 116/120 doc id 14395 rev 7 22-aug-2008 rev 2 cont?d ta bl e 4 9 : removed acc hsi parameters and replaced with acc hs parameters; amended data and footnotes. amended data of ? ram and hardware registers ? table. ta bl e 5 1 : updated names and data of n rw and t ret parameters. ta bl e 5 4 : added v oh and v ol parameters; updated i lkg ana parameter. removed: output driving current (standard ports) , output driving current (true open drain ports) , and output driving current (high sink ports) . ta bl e 5 9 : updated f adc , t s , and t conv data. adc accuracy for v dda = 3.3 v table : removed the 4-mhz condition from all parameters. ta bl e 6 0 : removed the 4-mhz condition from all parameters; updated footnote 1 and removed footnote 2. ta bl e 6 4 : added data for t a = 145 c. figure 50 : updated memory size, pin count and package type information. 16-sep-2008 rev 3 replaced the salestype ?stm8h61 xx? with ?stm8ah61xx on the first page. added ?part numbers? to heading rows of table 1: device summary . updated the 80-pin package silhouette on page 1 in line with poa 0062342-revd. ta bl e 1 6 : renamed ?tmu key registers 0-7 [7:0]? as ?tmu key registers 1-8 [7:0]? section 9 : updated introductory text concerning option bytes which do not need to be saved in a complementary form. ta bl e 1 6 : renamed the option bits ?t mu[0:3]?, ?ntmu[0:3]?, and ?tmu_key 0-7 [7:0]? as ?tmu[3:0]?, ?ntmu[3:0] ?, and ?tmu_key 1-8 [7:0]? respectively. ta bl e 3 5 : updated values of option byte 5 (hsecnt[7:0]); inverted the description of option byte 6 (tmu[3:0]); renamed option bytes 8 to 15 ?tmu_key 0-7 [7:0]?, as ?tmu_key 1-8 [7:0]?. updated 80-pin package information in line with poa 0062342-revd in figure 46 and ta bl e 6 6 . table 71. document revision history (continued) date revision changes
stm8af52/62xx, stm8af51/61xx revision history doc id 14395 rev 7 117/120 01-jul-2009 rev 4 added ?stm8ah61xx? and ?stm8ah51xx to document header. updated features on page 1 (memories, timers, operating temperature, adc and i/os). updated table 1: device summary updated kbytes value of program memory in chapter 1: introduction chapter 2: description ? changed the first two lines from the top. updated figure 1: stm8a block diagram updated chapter 5: product overview in figure 5: lqfp 48-pin pinout , added usart function to pins 10, 11, and 12; added can tx and can rx functions to pins 35 and 36 respectively. section 6.2: pin description ? deleted text below the table 8: legend/abbreviation for table 9 table 9: stm8a microcontroller family pin description ? 68th, 69th pin (lqfp80): repl aced x with a dash for pp output ? added a table footnote updated figure 7: register and memory map table 10: memory model 128k ? updated footnote deleted the table ?stack and ram partitioning? table 33: stm8a interrupt table . ? updated priorities 13, 15, 17, 20 and 24 ? changed table footnote updated chapter 7.2: register map updated table 53: data memory , table 54: i/o static characteristics , and table 55: nrst pin characteristics . section 10.1.1: minimum and maximum values . ? added ambient temperature t a = -40 c updated table 36: voltage characteristics updated table 37: current characteristics updated table 38: thermal characteristics updated table 40: general operating conditions updated table 41: operating conditions at power-up/power-down . figure 12: fcpumax versus vdd . ? updated temperature ranges in functional area ? added a figure footnote removed ? total current consumption ? and ? note on the run-current typical values ?. replaced table 42: total current consumption in run, wait and slow mode. general conditions for vdd apply. ta = -40 c to 150 c replaced table 43: total current consumption in halt and active halt modes. general conditions for vdd apply. ta = -40 c to 55 c unless otherwise stated . removed table 21: total current consumption in run, wait and slow mode. general conditions for v dd apply. t a = -40 c to 145 c table 71. document revision history (continued) date revision changes
revision history stm8af52/62xx, stm8af51/61xx 118/120 doc id 14395 rev 7 01-jul-2009 rev 4 removed table 22: total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 3.3 v. added table 44: oscillator current consumption added table 45: programming current consumption . updated table 46: typical peripheral current consumption vdd = 5.0 v changed section : hse external clock title from ?hse user external clock? updated table 47: hse external clock characteristics updated table 48: hse oscillator characteristics . figure 21: hse oscillator circuit diagram . ? changed ?consumption control? to ?current control? hse oscillator critical gm formula . ? clarified formula updated table 49: hsi oscillator characteristics . removed ? ram and hardware registers ? removed table 29: ram and hardware registers . updated table 51: flash program memory/data eeprom memory . added table 52: program memory added table 53: data memory . updated table 54: i/o static characteristics updated table 55: nrst pin characteristics updated table 56: tim 1, 2, 3, and 4 electrical specifications section 10.3.9: spi interface changed title from ?spi serial peripheral interface? updated table 57: spi characteristics . figure 41: spi timing diagram in slave mode and with cpha = 0 ? changed title ? added footnote 1 . figure 42: spi timing diagram in slave mode and with cpha = 1 ? changed title updated table 59: adc characteristics . updated figure 44: typical application with adc and added legend. removed table 36: adc accuracy for v dda = 3.3 v updated table 60: adc accuracy for vdda = 5 v updated table 62: emi data updated table 64: electrical sensitivities added section 11.1: ecopack? . figure 47: 64-pin low profile quad flat package (10 x 10) ? deleted footnote updated figure 50: ordering information scheme(1) . added chapter 13: known limitations . 22-oct-2009 rev 5 updated table 1: device summary : ? added stm8af5178, stm8af519a and stm8af619a. table 71. document revision history (continued) date revision changes
stm8af52/62xx, stm8af51/61xx revision history doc id 14395 rev 7 119/120 13-apr-2010 rev 6 updated title on cover page. modified cover page header to clarify the part numbers covered by the datasheets. updated note 1 below table 1: device summary to add ?p? order codes. changed definition of ?p? order codes. ?q? order codes (fastrom and eeprom) removed. content of section 5: product overview reorganized. table 9: stm8a microcontroller family pin description : updated pd7/tli alternate function, removed caution note for pd6/ linuart_rx, and added note 1 to pa1/oscin. renamed section 7 memory and register map , and content merged with section 9. register map. updated figure 7: register and memory map . renamed bl_en and nbl_en, bl and nbl, respectively, in table 34: option bytes . updated afr4 definition in table 35: option byte description .added c ext in table 40: general operating conditions , and section 10.3.1: vcap external capacitor . update t vdd in table 41: operating condit ions at power-up/power- down . moved table 46: typical peripheral current consumption vdd = 5.0 v to section : current consumption for on-chip peripherals . removed v esd(mm) from table 63: esd absolute maximum ratings . updated section 12: ordering information to the devices supported by the datasheet. updated section 13: known limitations . 08-jul-2010 rev 7 added stm8af5168 and stm8af518a part number in figure 4 , and stm8af618a in figure 5 . added stm8af52xx, stm8af6269, stm8af628x, and stm8af62ax. updated d temperature range to -40 to 150c. updated number of i/os on cover page. added table 39: operating lifetime . restored v esd(mm) from table 63: esd absolute maximum ratings . table 40: general operating conditions : updated v cap information. esl parameter, and range d maximum junction temperature (t j ). added stm8af52xx and stm8af62xx, and note 3 in section 12: ordering information . updated section 13: known limitations : added table 70: product evolution summary , and split the becan time triggered communication mode limitation into section 13.7.3 and section 13.7.4 . table 71. document revision history (continued) date revision changes
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